Physics to Tapeout: The Challenge of Scaling Reliability Verification

Srinivasan, Sridhar; Hogan, Matthew

doi:10.1109/irps.2019.8720440

Cited by 2 publications

(2 citation statements)

References 6 publications

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“…The table below shows the results of wire capacitance and resistance with the unit length of 1µm. In addition, the delay of each metal layer is computed by the following formula: t delay = 4 * RC (10) Based on the results above, the resistance and capacitance of a net will be calculated as the following formulas: R = length.R unitlength (11) C = length.C unitlength (12) The tool in the timing analysis stage, especially the synthesis stage will calculate the capacitance and resistance of a interconnect net based on the particular length value.…”

Section: Power Modelsmentioning

confidence: 99%

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A Novel Approach to Design a Process Design Kit Digital for CMOS 180nm Technology

Cong¹,

Le-Thanh²,

Bao³

et al. 2021

Adv. sci. technol. eng. syst. j.

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In this paper, a novel approach to design a Process Design Kit Digital for CMOS 180nm process is presented. This work proposes a detailed flow to design a PDK Digital using Ocean language, which is a vital element in the semi-custom design and applied in education purposes in universities in Vietnam. The PDK digital includes Standard Cell Library containing 47 standard cells and Wire-Load Model. The library is designed based on the CMOS 180nm process with a supply voltage of 1.8V.

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Section: Power Modelsmentioning

confidence: 99%

“…Focusing on the PDK digital, the one consists of Synopsys library and P&R library [10]. While the former is applied for timing, power consumption, and noise analysis, the latter is used for place and route design in a design flow [11]. There are two ways to design an SCL.…”

Section: Introductionmentioning

confidence: 99%