Picosecond multilevel resistive switching in tantalum oxide thin films

Böttger, U.; Witzleben, Moritz von; Havel, Viktor; Fleck, K.; Rana, Vikas; Waser, Rainer; Menzel, Stephan

doi:10.1038/s41598-020-73254-2

Cited by 54 publications

(51 citation statements)

References 51 publications

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“…Noticeably, the onset of the SET probability curve shifts to lower voltages when increasing the pulse duration. This phenomenon has been studied before and reflects the typical SET switching kinetics (Fleck et al, 2016;Witzleben et al, 2017;Nishi et al, 2018;Cüppers et al, 2019;Bengel et al, 2020;Böttger et al, 2020). However, the voltage range, where the probability is neither 0 nor 100%, remains roughly constant at around 160 mV, with some deviations caused by the limited number of tries.…”

Section: Cycle-to-cycle Switching Stochasticity Over Multiple Orders Of Magnitude In Switching Timesupporting

confidence: 54%

Utilizing the Switching Stochasticity of HfO2/TiOx-Based ReRAM Devices and the Concept of Multiple Device Synapses for the Classification of Overlapping and Noisy Patterns

et al. 2021

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With the arrival of the Internet of Things (IoT) and the challenges arising from Big Data, neuromorphic chip concepts are seen as key solutions for coping with the massive amount of unstructured data streams by moving the computation closer to the sensors, the so-called “edge computing.” Augmenting these chips with emerging memory technologies enables these edge devices with non-volatile and adaptive properties which are desirable for low power and online learning operations. However, an energy- and area-efficient realization of these systems requires disruptive hardware changes. Memristor-based solutions for these concepts are in the focus of research and industry due to their low-power and high-density online learning potential. Specifically, the filamentary-type valence change mechanism (VCM memories) have shown to be a promising candidate In consequence, physical models capturing a broad spectrum of experimentally observed features such as the pronounced cycle-to-cycle (c2c) and device-to-device (d2d) variability are required for accurate evaluation of the proposed concepts. In this study, we present an in-depth experimental analysis of d2d and c2c variability of filamentary-type bipolar switching HfO2/TiOx nano-sized crossbar devices and match the experimentally observed variabilities to our physically motivated JART VCM compact model. Based on this approach, we evaluate the concept of parallel operation of devices as a synapse both experimentally and theoretically. These parallel synapses form a synaptic array which is at the core of neuromorphic chips. We exploit the c2c variability of these devices for stochastic online learning which has shown to increase the effective bit precision of the devices. Finally, we demonstrate that stochastic switching features for a pattern classification task that can be employed in an online learning neural network.

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Section: Cycle-to-cycle Switching Stochasticity Over Multiple Orders Of Magnitude In Switching Timesupporting

confidence: 54%

Utilizing the Switching Stochasticity of HfO2/TiOx-Based ReRAM Devices and the Concept of Multiple Device Synapses for the Classification of Overlapping and Noisy Patterns

et al. 2021

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“…In consequence, overcoming this dilemma requires a strong non-linear dependence of the switching time on the applied voltage. In our recent publication, we have shown that the SET time of VCM devices depends indeed strongly non-linearly on the applied voltage in the range from 250 ps to 10 4 s [5], which is sufficient to address the voltagetime-dilemma.…”

Section: Introductionmentioning

confidence: 94%

Determining the Electrical Charging Speed Limit of ReRAM Devices

Witzleben

Walfort

Waser

et al. 2021

IEEE J. Electron Devices Soc.

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Redox-based random-access memory (ReRAM) has the potential to successfully address the technological barriers that today's memory technologies face. One of its promising features is its fast switching speed down to 50 ps. Identifying the limiting process of the switching speed is, however, difficult. At sub-nanosecond timescales three candidates are being discussed: An intrinsic limitation, being the migration of mobile donor ions, e.g. oxygen vacancies, the heating time, and its electrical charging time. Usually, coplanar waveguides (CPW) are used to bring the electrical stimuli to the device. Based on the data of previous publications, we show, that the rise time of the effective electrical stimulus is mainly responsible for limiting the switching speed at the sub-nanosecond timescale. For this purpose, frequency domain measurements up to 40 GHz were conducted on three Pt\TaOx\Ta devices with different sizes. By multiplying the obtained scattering parameters of these devices with the Fourier transform of the incoming signal, and building the inverse Fourier transform of this product, the voltage at the ReRAM device can be determined. Finally, the rise time of the voltage at the ReRAM device is calculated, which is a measure to the electrical charging time. It was shown that this rise time amounts to 2.5 ns for the largest device, which is significantly slower than the pulse generator's rise time. Reducing the device's rise time down to 66 ps is possible, but requires smaller features sizes and other optimizations, which we summarize in this paper.

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“…To predict the power consumption of our memristive circuit approach in realistic applications in IoT devices, we replaced the original transistor model in Verilog-A with a model corresponding to the 22-nm silicon-on-insulator (SOI) process with a channel length of ∼20 nm, close to the state-of-the-art. The switching speed of the memristor was also adapted to 10 ps, according to indications of switching dynamics found in similar devices [18]. The test circuit consists of a fan-out-of-4 (FO4) memristive inverters.…”

Section: Memristive Circuits For Iot Devicesmentioning

confidence: 99%

Threshold Switching Enabled Sub-pW-Leakage, Hysteresis-Free Circuits

Cheng

Emboras

Passerini

et al. 2021

IEEE Trans. Electron Devices

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In this article, we present ultralow leakage logic circuits by combining 3-D memristors with CMOS transistors. Significant leakage current reductions of up to 99% are found by experiments and simulation for a memristive hybrid-inverter if compared with a conventional inverter. Likewise, circuit simulations of memristive hybrid ring oscillators, NAND, or full adders show more than 100% gain in energy efficiency per cycle over state-ofthe-art circuits. Importantly, the memristive circuits offer hysteresis-free operation. The hysteresis-free operation is due to properly engineered properties-such as the threshold voltage-of the memristors to match the circuit, as well as the self-adaptive filament diameter of our memristor during operation. Lastly, the memristors feature a 10 8 ON-OFF ratio, enabling both high speed and low leakage (∼10 fA) when integrated with a transistor. They also come with a well-controlled filament formation on a ∼10-nm footprint, making them ideal to integrate with modern CMOS technology transistors.

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Picosecond multilevel resistive switching in tantalum oxide thin films

Cited by 54 publications

References 51 publications

Utilizing the Switching Stochasticity of HfO2/TiOx-Based ReRAM Devices and the Concept of Multiple Device Synapses for the Classification of Overlapping and Noisy Patterns

Utilizing the Switching Stochasticity of HfO2/TiOx-Based ReRAM Devices and the Concept of Multiple Device Synapses for the Classification of Overlapping and Noisy Patterns

Determining the Electrical Charging Speed Limit of ReRAM Devices

Threshold Switching Enabled Sub-pW-Leakage, Hysteresis-Free Circuits

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