2016 International Conference on Wireless Communications, Signal Processing and Networking (WiSPNET) 2016
DOI: 10.1109/wispnet.2016.7566517
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Pipeline and parallel processor architecture for fast computation of 3D-DWT using modified lifting scheme

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Cited by 4 publications
(1 citation statement)
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“…Interpolation with FPGAs have been used for video scaling [590][591][592] and motion estimator for High Efficient Video Coding (HEVC) encoder [593][594][595]. Other digital signal processing implementations in FPGAs includes lifting scheme for efficient and modular DWT [596][597][598][599], efficient convolution techniques [600][601][602] and 3D convolution [603]. Finally, in our list is the jitter detection (deviation from true periodicity of a presumably periodic signal) using FPGAs [604], which includes jitter studies for 5G communications [301], Multi-Gigabit FPGA-Embedded Serial Transceivers [605], clock oscillators [606] and random number generators based on clocks signal jitter [607][608][609].…”
Section: Digital Signal Processingmentioning
confidence: 99%
“…Interpolation with FPGAs have been used for video scaling [590][591][592] and motion estimator for High Efficient Video Coding (HEVC) encoder [593][594][595]. Other digital signal processing implementations in FPGAs includes lifting scheme for efficient and modular DWT [596][597][598][599], efficient convolution techniques [600][601][602] and 3D convolution [603]. Finally, in our list is the jitter detection (deviation from true periodicity of a presumably periodic signal) using FPGAs [604], which includes jitter studies for 5G communications [301], Multi-Gigabit FPGA-Embedded Serial Transceivers [605], clock oscillators [606] and random number generators based on clocks signal jitter [607][608][609].…”
Section: Digital Signal Processingmentioning
confidence: 99%