Pipeline power reduction through single comparator-based clock gating

Wang, Wei; Tsao, Yu-Chi; Choi, Ken; Park, Seongmo; Chung, Moo-Kyoung

doi:10.1109/socdc.2009.5423921

Cited by 8 publications

(6 citation statements)

References 6 publications

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“…CG eliminates unnecessary clock cycle occurrences. Local Explicit Clock Enable (LECE) [37], [38], [39] is a method using ENABLE signal for 2:1 multiplexer or multiplexed D flip-flop to update the output on the rising edge of the clock only when the ENABLE signal is high as shown in Figure 4. The more bits are used as an input, the more ENABLE signals occur.…”

Section: Low Power Techniques At Rt-level 1) Low Power Clock Techniquesmentioning

confidence: 99%

A Reconfigurable CNN-Based Accelerator Design for Fast and Energy-Efficient Object Detection System on Mobile FPGA

Kim

Choi

2023

IEEE Access

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In limited-resource edge computing circumstances such as on mobile devices, IoT devices, and electric vehicles, the energy-efficient optimized convolutional neural network (CNN) accelerator implemented on mobile Field Programmable Gate Array (FPGA) is becoming more attractive due to its high accuracy and scalability. In recent days, mobile FPGAs such as the Xilinx PYNQ-Z1/Z2 and Ultra96, definitely have the advantage of scalability and flexibility for the implementation of deep learning algorithm-based object detection applications. It is also suitable for battery-powered systems, especially for drones and electric vehicles, to achieve energy efficiency in terms of power consumption and size aspect. However, it has the low and limited performance to achieve real-time processing. In this article, optimizing the accelerator design flow in the register-transfer level (RTL) will be introduced to achieve fast programming speed by applying low-power techniques on FPGA accelerator implementation. In general, most accelerator optimization techniques are conducted on the system level on the FPGA. In this article, we propose the reconfigurable accelerator design for a CNN-based object detection system on the register-transfer level on mobile FPGA. Furthermore, we present RTL optimization design techniques that will be applied such as various types of clock gating techniques to eliminate residual signals and to deactivate the unnecessarily active block. Based on the analysis of the CNN-based object detection architecture, we analyze and classify the common computing operation components from the Convolutional Neuron Network, such as multipliers and adders. We implement a multiplier/adder unit to a universal computing unit and modularize it to be suitable for a hierarchical structure of RTL code. The proposed system design was tested with Resnet-20 which has 23 layers and it was trained with the dataset, CIFAR-10 which provides a test set of 10,000 images in several formats, and the weight data we used for this experiment was provided from Tensil. Experimental results show that the proposed design process improves the power efficient consumption, hardware utilization, and throughput by 16%, up to 58%, and 15%, respectively.INDEX TERMS FPGA accelerator, CNN accelerator, RT level design techniques, low power techniques, reconfigurable accelerator, CNN-based object detection, low power consumption, high performance, mobile FPGA.

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Section: Low Power Techniques At Rt-level 1) Low Power Clock Techniquesmentioning

confidence: 99%

A Reconfigurable CNN-Based Accelerator Design for Fast and Energy-Efficient Object Detection System on Mobile FPGA

Kim

Choi

2023

IEEE Access

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“…Figure 3 shows two types of registers with and without an enable signal. Furthermore, Figure 3b represents a local explicit clock enable (LECE) [19][20][21]. The output Q is updated on the rising edge of the clock only when the ENABLE signal is high.…”

Section: Clock Gatingmentioning

confidence: 99%

“…Based on the comparison of I/O signals, the bus-specific clock gating (BSCG) technique [19][20][21] utilizes the clock gating technique and adjusts the EN signal as shown in Figure 5a. The previously introduced LECE technique can deactivate blocks that are unnecessarily active, thus allowing each block to be controlled in a low-power scenario.…”

Section: Bus-specific Clock Gatingmentioning

confidence: 99%

“…Traditionally, as one of the hardware level designs, register-transfer-level (RT-level) optimization is an effective methodology to reduce the dynamic power consumption of the system. Therefore, in this article, we describe the RT-level low-power techniques we demonstrated in our previous paper [19][20][21] and how to apply them to the real industry model used for real-time object detection. We evaluate the power consumption through a reliable experimental environment including an FPGA platform and ASIC design flow.…”

Section: Introductionmentioning

confidence: 99%

“…At the RT-level, in addition, the developer is able to rearrange the processing schedule, reconfigure the circuit integration, and reconstruct the circuit logic elements for power reduction. A representative low-power technique is the clock gating technique [20]. Y. Chen et al discovered the power breakdown factors of the chip running layer in each convolution layer.…”

Section: Introductionmentioning

confidence: 99%

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Low-Power RTL Code Generation for Advanced CNN Algorithms toward Object Detection in Autonomous Vehicles

Kim

Yadav

et al. 2020

Electronics

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In the implementation process of a convolution neural network (CNN)-based object detection system, the primary issues are power dissipation and limited throughput. Even though we utilize ultra-low power dissipation devices, the dynamic power dissipation issue will be difficult to resolve. During the operation of the CNN algorithm, there are several factors such as the heating problem generated from the massive computational complexity, the bottleneck generated in data transformation and by the limited bandwidth, and the power dissipation generated from redundant data access. This article proposes the low-power techniques, applies them to the CNN accelerator on the FPGA and ASIC design flow, and evaluates them on the Xilinx ZCU-102 FPGA SoC hardware platform and 45 nm technology for ASIC, respectively. Our proposed low-power techniques are applied at the register-transfer-level (RT-level), targeting FPGA and ASIC. In this article, we achieve up to a 53.21% power reduction in the ASIC implementation and saved 32.72% of the dynamic power dissipation in the FPGA implementation. This shows that our RTL low-power schemes have a powerful possibility of dynamic power reduction when applied to the FPGA design flow and ASIC design flow for the implementation of the CNN-based object detection system.

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Low‐Power Computing

Vos

2010

Reversible Computing

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Pipeline power reduction through single comparator-based clock gating

Cited by 8 publications

References 6 publications

A Reconfigurable CNN-Based Accelerator Design for Fast and Energy-Efficient Object Detection System on Mobile FPGA

A Reconfigurable CNN-Based Accelerator Design for Fast and Energy-Efficient Object Detection System on Mobile FPGA

Low-Power RTL Code Generation for Advanced CNN Algorithms toward Object Detection in Autonomous Vehicles

Low‐Power Computing

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