Pipeline vectorization

Weinhardt, Markus; Luk, Wayne

doi:10.1109/43.908452

Cited by 113 publications

(62 citation statements)

References 20 publications

(29 reference statements)

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“…Pipeline vectorization, proposed by Weinhardt et al [68], is a typical dynamic method for loop parallelization at run time. It exploits the potential of pipelined hardware and combines the results of loop parallelization.…”

Section: Pipeline Parallelizationmentioning

confidence: 99%

A Survey of Loop Parallelization: Models, Approaches, and Recent Developments

Ye¹,

Deng²,

Zou³

2016

IJGDC

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In cloud computing era, automatic parallelization is still significant for virtualization platform. However, after several decades of development, the overall effect is still to be improved. Summary of the mainstream technology developments will be beneficial to reveal the future direction and trend. This paper reviews the technology of loop parallelization, which is the key issue in automatic parallelization. After introducing the basic models and approaches, we focus on the recent developments, on which we obtain the trend of this field and the conclusions about future.

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Section: Pipeline Parallelizationmentioning

confidence: 99%

A Survey of Loop Parallelization: Models, Approaches, and Recent Developments

Ye¹,

Deng²,

Zou³

2016

IJGDC

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“…This approach does not analyze task dependency in different iterations which may result in reduced parallelism. [1,2] Control flow based GCD, counter, Filtering Multiprocessors system not addressed [3] Modulo scheduling DCT, FFT Analyze one iteration, single loop [4] Graph conversion Random graphs Less parallelism, single loop [5][6][7] Loop unrolling Random graphs, FFT, solver equalizer Single loop unrolling [8] Dynamic scheduling Fractal generation Loop unrolling not addressed, single loop [9,10] Loop fission JPEG compression, DCT, BPIC Loop unrolling not addressed, single loop…”

Section: Introductionmentioning

confidence: 99%

Multiloop Parallelisation Using Unrolling and Fission

Lam

Coutinho

et al. 2010

International Journal of Reconfigurable Computing

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A technique for parallelising multiple loops in a heterogeneous computing system is presented. Loops are first unrolled and then broken up into multiple tasks which are mapped to reconfigurable hardware. A performance-driven optimisation is applied to find the best unrolling factor for each loop under hardware size constraints. The approach is demonstrated using three applications: speech recognition, image processing, and the N-Body problem. Experimental results show that a maximum speedup of 34 is achieved on a 274 MHz FPGA for the N-Body over a 2.6 GHz microprocessor, which is 4.1 times higher than that of an approach without unrolling.

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“…Shorter computing time implies less power consumption. Existing signal and image processing algorithms to FPGA mapping tools/methodologies include [7]- [9] and [10]. They all focus on the previous generation of FPGAs.…”

Section: Introductionmentioning

confidence: 99%

“…Hence, the computation throughput is increased. In addition to Matlab, Einhardt, and Luk [9] target at loops written in C programming language. Finally, DG2VHDL [10] is a VHDL generator of the hardware counterpart of a nested loop algorithm.…”

Section: Introductionmentioning

confidence: 99%

Mapping deep nested do-loop DSP algorithms to large scale FPGA array structures

Kittitornkun

2003

IEEE Trans. VLSI Syst.

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Abstract-Recently, FPGAs (field programmable gate arrays) technology have made significant advances in both speed and capacity. Millions of logic gates are now available for reconfiguration programming. To fully exploit the potential of so many programmable devices, powerful design methodology must be developed. In this paper, we propose a novel systematic computer-aided design methodology that can efficiently implement deeply nested do-loop algorithms on a FPGA. Specifically, our design methodology maps the loop dependence graph onto a linear array of locally connected processing elements to exploit parallelism. Due to the regular structure of this linear array of processors, it can be easily implemented on a FPGA. While this method is based on conventional systolic array design methodology, our proposed approach exhibits two distinct features that contribute to its superior performance: 1) We developed a novel multiple-order dependence graph representation that is able to efficiently represent distinct, yet correct algorithm execution orders. 2) We developed new FPGA-specific architectural constraints during the mapping process. As such, FPGA implementations based on our approach will utilize much fewer lookup tables while achieving superior performance.

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Pipeline vectorization

Cited by 113 publications

References 20 publications

A Survey of Loop Parallelization: Models, Approaches, and Recent Developments

A Survey of Loop Parallelization: Models, Approaches, and Recent Developments

Multiloop Parallelisation Using Unrolling and Fission

Mapping deep nested do-loop DSP algorithms to large scale FPGA array structures

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