Pipelined Block-Serial Decoder Architecture for Structured Ldpc Codes

Bhatt, T.; Sundaramurthy, Vishwas; Stolpman, V.; McCain, D.

doi:10.1109/icassp.2006.1660946

Cited by 27 publications

(17 citation statements)

References 5 publications

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“…However, processing of a single sub-matrix in isolation only requires a simple local communication network (switch) and a simple memory structure [22,1,6,29,25]. It does not solve the problem of an effective and efficient processing of the whole PCM matrix and related communication architecture for this aim.…”

Section: Case Study: Communication Architectures Of Ldpc Decodersmentioning

confidence: 98%

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Scalable communication architectures for massively parallel hardware multi-processors

Jan

Jówiak

2012

Journal of Parallel and Distributed Computing

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Section: Case Study: Communication Architectures Of Ldpc Decodersmentioning

confidence: 98%

“…In the past, several partially-parallel architectures have been proposed for the LDPC decoding [22,1,6,29,25,13,26,21]. However, they only deliver a throughput of a few hundreds of Mbps.…”

Section: Related Researchmentioning

confidence: 98%

Scalable communication architectures for massively parallel hardware multi-processors

Jan

Jówiak

2012

Journal of Parallel and Distributed Computing

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“…(7) with a simple subtract operation, similar to serial or merged LDPC decoding schedule [4]. The semi-parallel Zigzag decoding is similar to layered LDPC decoding [4]- [6]. The parallelization of the forward pass of the Zigzag decoding sub-iteration is depicted 100 where, (8) in Fig.…”

Section: Zigzag Codesmentioning

confidence: 98%

Structured Interleavers and Decoder Architectures for Zigzag Codes

Bhatt

Stolpman

2006

2006 Fortieth Asilomar Conference on Signals, Systems and Computers

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We propose structured interleaver design for parallel concatenated Zigzag codes. While the proposed design performs as good as or better than random interleavers for various block-sizes, it improves the error floor of the Zigzag codes and offers a lot of parallelism suitable for high data-rate applications. The interleaver can be specified with only a few parameters and can be efficiently implemented in both hardware and software. We also evaluate semi-parallel Zigzag decoder architecture that exploits the parallelism of the proposed interleavers to improve the throughput. We also evaluate the performance of an efficient decoding schedule for semi-parallel Zigzag decoder that provides better throughput and performance trade-offs compared to the fully parallel and serial decoder schedule. The proposed interleaver scheme and architecture are suitable for high throughput Ultra Wideband communications that demand data-rates up to several hundred mbps.

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“…High-speed flexible LDPC decoder architectures are well-known in the art [17], [18], [19], [20], and the principle for estimating a latency of iterative receiver with soft sphere detection is independent of decoding scheme. The codeword size for the outer LDPC decoder is assumed to be 1944 bits which is one particular specification for the emerging IEEE 802.11n standard [21], the code rate is 1/2, maximum number of inner iterations of layered belief propagation algorithm is 15.…”

Section: Iterative Receivers For Emerging Wireless Standards: Harmentioning

confidence: 99%

“…After combining (15), (16), and (17), we derive a relation between the area cost of the iterative detectiondecoding part of the receiver and desired data throughput T hr as in (18).…”

Section: Iterative Receivers For Emerging Wireless Standards: Harmentioning

confidence: 99%

Probabilistically bounded soft sphere detection for MIMO-OFDM receivers: algorithm and system architecture

Radosavljevic¹,

Guo

Cavallaro

2009

IEEE J. Select. Areas Commun.

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Abstract-Iterative soft detection and channel decoding for MIMO OFDM downlink receivers is studied in this work. Proposed inner soft sphere detection employs a variable upper bound for number of candidates per transmit antenna and utilizes the breath-first candidate-search algorithm. Upper bounds are based on probability distribution of the number of candidates found inside the spherical region formed around the received symbolvector. Detection accuracy of unbounded breadth-first candidatesearch is preserved while significant reduction of the search latency and area cost is achieved. This probabilistically bounded candidate-search algorithm improves error-rate performance of non-probabilistically bounded soft sphere detection algorithms, while providing smaller detection latency with same hardware resources. Prototype architecture of soft sphere detector is synthesized on Xilinx FPGA and for an ASIC design. Using area-cost of a single soft sphere detector, a level of processing parallelism required to achieve targeted high data rates for future wireless systems (for example, 1 Gbps data rate) is determined.

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Pipelined Block-Serial Decoder Architecture for Structured Ldpc Codes

Cited by 27 publications

References 5 publications

Scalable communication architectures for massively parallel hardware multi-processors

Scalable communication architectures for massively parallel hardware multi-processors

Structured Interleavers and Decoder Architectures for Zigzag Codes

Probabilistically bounded soft sphere detection for MIMO-OFDM receivers: algorithm and system architecture

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