Pipelined Decision Tree Classification Accelerator Implementation in FPGA (DT-CAIF)

Saqib, Fareena; Dutta, Aindrik; Plusquellic, Jim; Ortiz, P.; Pattichis, Marios S.

doi:10.1109/tc.2013.204

Cited by 81 publications

(42 citation statements)

References 17 publications

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“…Many TM overlays have large area overheads due to the routing resources, or large instruction storage requirements. To address these problems, we propose a streaming architecture based on feed-forward pipelined datapaths, as streaming based accelerators have been highly successful when implemented in FPGAs [18], [23]. Targeting highly compute intensive algorithms with little control and relatively simple dependencies allows us to use a linear interconnect structure, where data flows in a single direction from one FU to the next, thus minimizing the interconnect requirements.…”

Section: Related Workmentioning

confidence: 99%

“…Similarly for the 2nd cluster, scheduling as: 14,26,21,10,16,11,27,22, resolves dependencies 14-11, 26-27, and 21-22, for all overlay versions. In cluster three, scheduling as: 18,24,28,23,19,30,8, resolves all dependencies for the V4 and V5 overlays, but not for the V3 overlay, which with an IWP of 5 requires 4 operations between dependant nodes. Hence, a single NOP must be added between 23 and 19 which then resolves all 4 sets of dependant instructions.…”

Section: Compiling To the Overlaymentioning

confidence: 99%

See 1 more Smart Citation

A time-multiplexed FPGA overlay with linear interconnect

Jain

Maskell

et al. 2018

2018 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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Coarse-grained overlays improve FPGA design productivity by providing fast compilation and software like programmability. Soft processor based overlays with well-defined ISAs are attractive to application developers due to their ease of use. However, these overlays have significant FPGA resource overheads. Time multiplexed (TM) CGRA-like overlays represent an interesting alternative as they are able to change their behavior on a cycle by cycle basis while the compute kernel executes. This reduces the FPGA resource needed, but at the cost of a higher initiation interval (II) and hence reduced throughput.The fully flexible routing network of current CGRA-like overlays results in high FPGA resource usage. However, many application kernels are acyclic and can be implemented using a much simpler linear feed-forward routing network. This paper examines a DSP block based TM overlay with linear interconnect where the overlay architecture takes account of the application kernels' characteristics and the underlying FPGA architecture, so as to minimize the II and the FPGA resource usage. We examine a number of architectural extensions to the DSP block based functional unit to improve the II, throughput and latency. The results show an average 70% reduction in II, with corresponding improvements in throughput and latency.

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Section: Related Workmentioning

confidence: 99%

Section: Compiling To the Overlaymentioning

confidence: 99%

A time-multiplexed FPGA overlay with linear interconnect

Jain

Maskell

et al. 2018

2018 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

View full text Add to dashboard Cite

show abstract

“…Process of CART classification is the process that the training set is divided into smaller and smaller subsets [21][22][23]. The ideal result is that there is the same tag to leaf node samples of generate tree.…”

Section: Classification Algorithm Of Cart Decision Treementioning

confidence: 99%

A Classification Algorithm of CART Decision Tree based on MapReduce Attribute Weights

Zhu¹

2018

IJPE

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A CART decision tree algorithm based on attribute weight is proposed in this paper because of the present problems of complex classification, poor accuracy, low efficiency, and severe memory consumption of CART decision. What is more, the algorithm is combined with the parallel computing model of MapReduce. Theory of attribute weights is used in the algorithm. A decision tree is built through the sum of weights, which is decided by the degree that the attributes affect a decision. Thus the accuracy of classification through decision tree is improved. Parallel sorting algorithms of CART decision tree for massive data is implemented through the MapReduce programming technology of cloud computing. All the results of theoretical analysis and experimental comparison show that it is very important to mark attributes by weights through MapReduce. Furthermore, the accuracy of the classification of large sample data sets is improved significantly, classification efficiency of decision tree is improved and the trained time is also significantly reduced.

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“…The decision tree classification technique is one of the important toolsets in data mining and has been widely used in many fields, such as biology, computer science and technology, clinical medicine, geology, management science and engineering [43][44][45][46][47]. In accordance with the top-down induction of decision tree, a DT consists of some root nodes, which are then split into more branches [48].…”

Section: C45 Decision Tree Classificationmentioning

confidence: 99%

Evaluation of the Consistency of MODIS Land Cover Product (MCD12Q1) Based on Chinese 30 m GlobeLand30 Datasets: A Case Study in Anhui Province, China

Liang

Zuo

Huang

et al. 2015

IJGI

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Abstract:Land cover plays an important role in the climate and biogeochemistry of the Earth system. It is of great significance to produce and evaluate the global land cover (GLC) data when applying the data to the practice at a specific spatial scale. The objective of this study is to evaluate and validate the consistency of the Moderate Resolution Imaging Spectroradiometer (MODIS) land cover product (MCD12Q1) at a provincial scale (Anhui Province, China) based on the Chinese 30 m GLC product (GlobeLand30). A harmonization method is firstly used to reclassify the land cover types between five classification schemes (International Geosphere Biosphere Programme (IGBP) global vegetation classification, University of Maryland (UMD), MODIS-derived Leaf Area Index and Fractional Photosynthetically Active Radiation (LAI/FPAR), MODIS-derived Net Primary Production (NPP), and Plant Functional Type (PFT)) of MCD12Q1 and ten classes of GlobeLand30, based on the knowledge rule (KR) and C4.5 decision tree (DT) classification algorithm. A total of five harmonized land cover types are derived including woodland, grassland, cropland, wetland and artificial surfaces, and four evaluation indicators are selected including the area consistency, spatial consistency, classification accuracy and landscape diversity in the three sub-regions of Wanbei, Wanzhong and Wannan. The results indicate that the consistency of IGBP is the best among the five schemes of MCD12Q1 according to the correlation coefficient (R). The "woodland" LAI/FPAR is the worst, with a spatial OPEN ACCESS ISPRS Int. J. Geo-Inf. 2015, 4 2520 similarity (O) of 58.17% due to the misclassification between "woodland" and "others". The consistency of NPP is the worst among the five schemes as the agreement varied from 1.61% to 56.23% in the three sub-regions. Furthermore, with the biggest difference of diversity indices between LAI/FPAR and GlobeLand30, the consistency of LAI/FPAR is the weakest. This study provides a methodological reference for evaluating the consistency of different GLC products derived from multi-source and multi-resolution remote sensing datasets on various spatial scales.

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Pipelined Decision Tree Classification Accelerator Implementation in FPGA (DT-CAIF)

Cited by 81 publications

References 17 publications

A time-multiplexed FPGA overlay with linear interconnect

A time-multiplexed FPGA overlay with linear interconnect

A Classification Algorithm of CART Decision Tree based on MapReduce Attribute Weights

Evaluation of the Consistency of MODIS Land Cover Product (MCD12Q1) Based on Chinese 30 m GlobeLand30 Datasets: A Case Study in Anhui Province, China

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