Pipelined Distributive Arithmetic-based FIR Filter Using Carry Save and Ripple Carry Adder

Saritha, M.; Radhika, C.; Reddy, Mulinti Narendra; Lavanya, M.; Karthik, A.; Vijay, Vallabhuni; Vallabhuni, Rajeev Ratna

doi:10.1109/c2i454156.2021.9689396

Cited by 11 publications

(16 citation statements)

References 18 publications

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“…Hence, there is drift in transistor manufacture from CMOS to FinFET technology. [27][28][29][30][31][32][33][34][35][36][37][38][39][40]…”

Section: Finfet Characteristics and Modellingmentioning

confidence: 99%

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Data Conversion: Realization of Code converter using Shift Register Modules

2023

VLSI

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Barrel shifter architecture is well known for bit manipulation in a single clock cycle. Due to its various operations and advantages, it is most likely used in the Arithmetic logic unit of every processor. Gray code is also known as reflective code which is widely used in digital communication for the purpose of error correction and error detection. In this project, an 8 x 4 barrel shifter is designed which is further connected to 4-bit binary to gray code converter. The barrel shifter is cascaded with binary to gray code converter so that this combination can be useful for the application of encryption of binary data in digital communications. It is designed in cadence virtuoso tool using FinFET technology at 18 nm node. The simulation results proves that the power consumed by the proposed design with FinFET technology is 11.92% less when compared with the conventional design with MOS transistors. Hence, this design can be used in application of low power digital communications. The functionality testing and verification is done using cadence virtuoso tool.

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“…Hence, there is drift in transistor manufacture from CMOS to FinFET technology. [27][28][29][30][31][32][33][34][35][36][37][38][39][40]…”

Section: Finfet Characteristics and Modellingmentioning

confidence: 99%

“…[11] To improve this architecture, its analysis is carried out using FinFET technology through this paper. [30][31][32][33][34][35][36][37][38][39]…”

mentioning

confidence: 99%

Data Conversion: Realization of Code converter using Shift Register Modules

2023

VLSI

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“…The lower range 10-bit and 4-bit comparators are designed with help of cascading 4-bit and 2-bit comparators. [15][16][17][18][19][20][21][22][23][24][25] The 32-bit comparator is designed and implemented using Cadence virtuoso tool at 180 nm technology and is compared with the Raman's Full adder based 32-bit comparator architecture. [7] The Proposed architecture of Full adder based 32-bit comparator is as shown in the Fig.…”

Section: Existing Comparatorsmentioning

confidence: 99%

Data Distinguisher Module Implementation using CMOS Techniques

2023

VLSI

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Comparator plays a vital role in many IC applications, Microprocessors, computer systems etc. Hence it is desirable to design a comparator block with low power consumption and high speed performance .In this paper a novel architecture of 32-bit comparator using Complementary metal-oxide semiconductor logic is proposed and computed its delay and power metrics. Further it is compared with the full adder based 32-bit comparator. From the analysis we derive the comparison between proposed and the conventional comparator. The complete designing of architectures and their result analysis was done in cadence virtuoso tool at 180 nm technology. Simulation results show that there is reduce in power consumption of 90% when compared to the conventional full adder based comparator.

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“…The subsequent gate of FinFET can be utilized to control the limit voltage of the gadget, accordingly permitting quick turning on one side and diminished leakage current when circuits are inactive. [12][13][14][15][16][17] SRAM is one among the recollections for the most part utilized in the storage memory of gadgets. Memory Cells (SRAM) need to be quicker, consume less power devouring and reliable.…”

Section: Introductionmentioning

confidence: 99%

Flip-Flop Realization: Conventional Memory Elements Design with Transistor Nodes

2023

VLSI

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In the ultra-low-power implementation, center circuits of numerous frameworks are activated by inadequate occasions, for example, the Internet of Things (IoT) sensors and implantable clinical consideration. To guarantee that, the sensors get each and every occasion showing up whenever the circuits operate in standby mode the most of the time. Under such conditions, static power dominates in the total power consumption. For these implementations, the lessening framework leakage current can straightforwardly accomplish the greatest effectiveness of the complete framework power utilization. Since the SRAM cluster takes up a bigger bit of the circuit, it is important to decrease the power utilization of the SRAM exhibit so as to lessen circuit all-out power. Band-to-band tunneling (BTBT) mechanism introduced silicon tunnel FET (TFET), MOSFET compatible fabrication process and ultra-steep SS, which can break the 60mV/dec limitation of MOSFET at room temperature and ultralow off-state current. Subsequently, it is required to be a promising contender for an ultra-low-power rationale circuit. The impact of forward p-I-n leakage current could prompt harm to the static noise margin (SNM), static power and power defer result of the SRAM circuit. So the proposed topology can stay away from the p-I-n intersection, by expanding SRAM cell read and hold static noise margin (SNM) and diminishing static power utilization drastically.

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Pipelined Distributive Arithmetic-based FIR Filter Using Carry Save and Ripple Carry Adder

Cited by 11 publications

References 18 publications

Data Conversion: Realization of Code converter using Shift Register Modules

Data Conversion: Realization of Code converter using Shift Register Modules

Data Distinguisher Module Implementation using CMOS Techniques

Flip-Flop Realization: Conventional Memory Elements Design with Transistor Nodes

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