Pipelined Error-detecting Codes in FPGA Testing

One of the main features of hash functions is a significant change in the hash with any (even small) changes in the input data. Using their pipelined versions (which outputs the next hash on each clock cycle) allows to create a system that is guaranteed to respond to any failures in the process. Reference systems based on control code generators can be quickly developed and thanks to a wide range of functions, for calculating control codes, can be close to the characteristics of the developed system in terms of area and logical complexity. In this article, we propose using pipelined control code generators as reference systems in the development of fault tolerant computing systems. In this case, before or simultaneously with the development of a computing system, we need to perform a series of experiments with pipelined generators and control codes. Several versions of such reference system have been developed, each of which implements various fault tolerance techniques. The obtained protected reference systems are synthesized into the basis of available FPGAs by various software packages. Next, the results are compared and the most successful (with good results) sets are selected from FPGAs, software, and fault tolerance techniques.

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Pipelined Error-detecting Codes in FPGA Testing

Cited by 2 publications

References 2 publications

Low-power DSSS transmitter and its VLSI implementation

Low-power DSSS transmitter and its VLSI implementation

Using pipelined control code generator as a reference system in FPGA’s selection as a hardware platform for fault-tolerance computing system

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