Pipelined Implementation of Dynamic Rijndael S-Box

Parmar, Nilima D.; Kadam, Poonam

doi:10.5120/19578-1384

Cited by 7 publications

(6 citation statements)

References 8 publications

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“…2 and 3, respectively. Besides, the Boolean equations of the multiplicative inversion in GF((2 2 ) 2 ) and post_processing are written as (13) and (14) (and (15)), respectively. Therefore, the proposed VLSI design can be simply implemented and replicated.…”

Section: Discussionmentioning

confidence: 99%

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VLSI Architecture of S-Box With High Area Efficiency Based on Composite Field Arithmetic

et al. 2022

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This work aims at optimizing the hardware implementation of the SubBytes and inverse SubBytes operations in the advanced encryption standard (AES). To this, the composite field arithmetic (CFA) is employed to optimize all building blocks in S-box (and inverse S-box) of SubBytes (and inverse SubBytes) transformation. A joint design of S-box and inverse S-box is also proposed to further enhance the area efficiency. Specifically, the area of multiplier in the Galois composite field, GF((2 2 ) 2 ), is reduced. The squaring and multiplication with constant λ in GF((2 2 ) 2 ) are combined and optimized as well. Moreover, the multiplicative inversion in GF((2 2 ) 2 ) is manually optimized. Furthermore, the S-box and inverse Sbox are combined and optimized using the pre_processing and post_processing modules. To increase the throughput, a balanced and pipelined architecture is derived. Using the proposed architecture, a throughput of 5.79 Gbps for the S-box can be achieved on Virtex-6 XC6VLX240T and 10% better than the conventional work. According to the ASIC implementation result, the proposed design can still achieve the highest area efficiency and approximately 30% better than conventional works using TSMC 90nm process.INDEX TERMS Advanced encryption standard (AES), Composite field arithmetic (CFA), S-box, VLSI architecture.

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Section: Discussionmentioning

confidence: 99%

“…The work [12] presented a S-box based on the multiplexer. The work [13] evaluated 5-, 6-, and 7-stages pipelined S-box based on the CFA. By contrast, the studies, [14] and [15], proposed a 4-stage pipelined S-box.…”

Section: Introductionmentioning

confidence: 99%

VLSI Architecture of S-Box With High Area Efficiency Based on Composite Field Arithmetic

et al. 2022

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“…Patel et al developed a low‐cost parallel architecture for the fast AES algorithm using VHDL. Parmar and Kadam designed a pipelined architecture for S‐Box of the AES algorithm. The experimental results demonstrate that the AES algorithm, with the pipelined S‐Box, performs well based on FPGA, and they can get higher throughput and less delay.…”

Section: Related Workmentioning

confidence: 99%

Implementation and optimization of a data protecting model on the Sunway TaihuLight supercomputer with heterogeneous many‐core processors

Chen

Fei

et al. 2018

Concurrency and Computation

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With the rapid development of information technology, the security of massive amounts of digital data has attracted huge attention in recent years. The Advanced Encryption Standard (AES) algorithm and the Security Hash Algorithm 3 (SHA3) are extensively used as cryptographic algorithms for protecting the security of information. The Sunway TaihuLight, with massive heterogeneous many-core SW26010 processors, has the peak performance of over 100 PFlops. To achieve high efficiency of data encryption/decryption and guarantee the data integrity for large-scale applications, this paper proposes a fast and secure data protecting model using the parallel AES algorithm and the SHA3 on the Sunway TaihuLight. According to the particular computing architecture and memory hierarchy of the Sunway TaihuLight, we propose a fine-grained software design for the data protecting model to fully exploit the parallelism and properly arranges the data on the Sunway. Furthermore, we propose optimization strategies for the parallel AES algorithm of the data protecting model. It is proved that our data protecting model has high security, good scalability, and excellent encryption/decryption efficiency on the Sunway. Our data protecting model achieves a high throughput of 269.95 Gbits/s, and the optimized parallel AES algorithm achieves 511.28 Gbits/s on the Sunway. KEYWORDSadvanced encryption standard (AES), heterogeneous many-core processor, parallelism, security hash algorithm 3 (SHA3), Sunway TaihuLight supercomputer INTRODUCTION MotivationIn recent years, many network platforms, such as micro-blog, forums, and e-commerce sites, have become increasingly popular. Large amount of digital data is generated and stored in the internet. As the activity of internet users progressively increases, we are faced with the risk of security and confidentiality of massive digital information. In addition, the growing number of incidences of data leakage leads serious impact and losses to the internet users, which makes the data security become the hot point and a major concern of the society. It is extremely urgent to figure out a way to provide a reliable and safe environment for internet users.Using the cryptographical technology is one of the key methods to ensure the security of digital data. In cryptography, the block cipher has strong applicability and security. It executes encryption and decryption on a set of fixed-size data blocks using a symmetric key. The Advanced Encryption Standard (AES) 1 is a block cipher extensively used by enterprises and organizations for protecting the security of information. However, the traditional AES encryption/decryption is a computationally intensive task, which leads to the inefficiency of encrypting/decrypting large-scale digital data. In addition, the traditional AES algorithm is unable to meet the demand of protecting massive data efficiently. Users cannot accept too much time spent on data encryption/decryption. Normally, the AES algorithm takes a 16-byte data block as input and performs several rounds o...

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“…Therefore, hardware accelerators-rather than software implemented on generalpurpose processors-are commonly used to improve the performance of AES processes to meet real-time processing requirements [7]. For efficient data transfer and storage, AES-based systems must exhibit high throughput [8], which can be achieved using field-programmable gate arrays [9], [10], [11] or application-specific integrated circuits (ASICs) [12], [13], [14], [15], [16]. Accordingly, to meet the requirement of high-throughput performance for communication security applications, the present study presents a highthroughput, seven-stage hardware pipeline architecture for SubByte computations in the AES for information security applications.…”

Section: Introductionmentioning

confidence: 99%

Hardware Implementation of High-Throughput S-Box in AES for Information Security

et al. 2023

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The Advanced Encryption Standard (AES) is used for achieving quantum-resistant cryptography when a 256-bit key is applied. This paper presents a high-throughput, seven-stage hardware pipeline architecture for SubByte computations in the AES for information security applications. Composite field arithmetic-based calculations are employed for logic optimization. The proposed architecture includes dedicated multistage multiplication processes based on Galois field polynomials for constants, squaring, and variables; thus, the critical path of SubByte computations is shortened, and the maximum operating frequency is enhanced. The proposed architecture was synthesized using a TSMC 40-nm cell library, and the throughput of the proposed architecture (34.78 Gbps) was observed to be superior to that of an existing state-of-the-art architecture by 43.47%. Moreover, our architecture was noted to consume lower dynamic power for combinational logic circuits, indicating that the proposed architecture has greater computational logic optimization than existing designs. The proposed architecture is feasible for communication security applications in the Internet of Things systems because of its high throughput and area efficiency.INDEX TERMS AES, hardware, high-throughput, information security, S-box.NARN-YIH LEE received the Ph.D. degree in information engineering from the National Cheng Kung University, Taiwan, in 1996. He is currently a Professor with the Computer and Network Center, National Cheng Kung University. His research interests include cryptography, blockchain, network security, post quantum cryptography, and chip security.

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Pipelined Implementation of Dynamic Rijndael S-Box

Cited by 7 publications

References 8 publications

VLSI Architecture of S-Box With High Area Efficiency Based on Composite Field Arithmetic

VLSI Architecture of S-Box With High Area Efficiency Based on Composite Field Arithmetic

Implementation and optimization of a data protecting model on the Sunway TaihuLight supercomputer with heterogeneous many‐core processors

Hardware Implementation of High-Throughput S-Box in AES for Information Security

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