Pipelined vedic multiplier with manifold adder complexity levels

Abstract

Recently, the increased use of portable devices, has driven the research world to design systems with low power-consumption and high throughput. Vedic multiplier provides least delay even in complex multiplications when compared to other conventional multipliers. In this paper, a 64-bit multiplier is created using the Urdhava Tiryakbhyam sutra in Vedic mathematics. The design of this 64-bit multiplier is implemented in five different ways with the pipelining concept applied at different stages of adder complexities. The different architectures show different delay and power consumption. It is noticed that as complexity of adders in the multipliers reduce, the systems show improved speed and least hardware utilization. The architecture designed using 2 x 2 – bit pipelined Vedic multiplier is, then, compared with existing Vedic multipliers and conventional multipliers and shows least delay.

Vedic-Based Squarers with High Performance

“…The current multipliers and squarers (precisely their related adders), which form the central part of these systems, affect their speed and area [18]. The more complex squarers and multipliers or their related adders are, the more they influence the rate and size [2,24].…”

“…The prime reason for the delay in squarers and multipliers is the propagation of carrying along the road to the squarer's most significant bit. When a Vedic technique such as UTS is utilized, the pipelined style can add the generated partial products [24]. Thus, it is observed that the VBS, which utilizing the UTS technique for squaring binary numbers, can produce outputs faster than other squarers by decreasing the delay to make the final result.…”