Pixel Design Driven Performance Improvement in 4T CMOS Image Sensors: Dark Current Reduction and Full-Well Enhancement

Abstract

Dark current limits the optical performance of CMOS image sensors. The main sources of the dark current in a modern submicron process are the defects induced by the shallow trench isolation fabrication process steps. In this paper, we present a pixel layout technique to reduce the impact of these defects by removing the trench-oxide between the two adjacent edges of neighbouring photodiodes. This isolation scheme relies on the p-well layer only and provides the further advantage of requiring less area. Hence, a larger photodiode can be designed, leading to an increased pixel fill factor. Experimental results show that this approach reduces the dark current by 21% and increases the linear full well capacity by approximately 9%.

All-Analog Silicon Integration of Image Sensor and Neural Computing Engine for Image Classification

“…nal voltage (i.e., S, the pixel output voltage at the end of integration), in order to cancel the thermal noise associated to the voltage on the PD capacitance (i.e., the so-called KTC noise). However, as opposed to the standard 4T pixel architecture[23], only a transfer gate (the one driven by the TG signal in Fig.4), reset (driven by the Rst signal) and a source-follower amplifier are used (driven by the floating diffusion FD node). The row-select transistor is not needed here, since all the 25 pixels are directly connected to the corresponding S&H blocks, 25 in total, each realized with two selectors and two MIM capacitors, to store the V pix in terms of R and S values, with R > S. This translates into the fact that all the 25 pixels can be exposed at the same time, in a global shutter mode, which is indeed feasible due to the extremely low resolution.…”