Pixel-parallel CMOS active pixel sensor for fast object location

Burns, R.D.; Thomas, Christopher; Thomas, Paul J.; Hornsey, Richard

doi:10.1117/12.506249

Cited by 6 publications

(4 citation statements)

References 5 publications

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“…The "artificial retina" approach has similar features in terms of processing possibilities [17]. These architectures are frequently developed to process a neighborhood of the pixels [1][2][3], however the process is usually reduced to small size neighborhoods (usually smaller than 16 × 16). The acquisition can be controlled, but is dependent on the architecture and the targeted applications.…”

Section: Context and Coprocessor Into Processing/acquistion Loopmentioning

confidence: 99%

“…The detection is based on the comparisons using the logical operator XNOR, which replaces the traditional matching criterion based on the sum of absolute difference (SAD). The binary correlation algorithm is defined as follows: (2) i and j between 0 and N − M. with S1 the binary shape (M × M size), S2 the binary search window (N × Nsize). Figure 6: Block diagram of the coprocessor component implementing local adaptive binarization process.…”

Section: Example Of Achievable Performancementioning

confidence: 99%

“…(i) Artificial retinas: in which dedicated processing is directly integrated aside the pixel. The processing capabilities are usually fixed or limited to a few simple and local functions [1][2][3].…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Smart Camera Based on Embedded HW/SW Coprocessor

Mosqueron¹,

Dubois²,

Mattavelli³

et al. 2008

EURASIP Journal on Embedded Systems

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This paper describes an image acquisition and a processing system based on a new coprocessor architecture designed for CMOS sensor imaging. The system exploits the full potential CMOS selective access imaging technology because the coprocessor unit is integrated into the image acquisition loop. The acquisition and coprocessing architecture are compatible with the majority of CMOS sensors. It enables the dynamic selection of a wide variety of acquisition modes as well as the reconfiguration and implementation of high-performance image preprocessing algorithms (calibration, filtering, denoising, binarization, pattern recognition). Furthermore, the processing and data transfer, from the CMOS sensor to the processor, can be operated simultaneously to increase achievable performances. The coprocessor architecture has been designed so as to obtain a unit that can be configured on the fly, in terms of type and number of chained processing stages (up to 8 successive predefined preprocessing stages), during the image acquisition process that can be defined by the user according to each specific application requirement. Examples of acquisition and processing performances are reported and compared to classical image acquisition systems based on standard modular PC platforms. The experimental results show a considerable increase of the achievable performances.

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Section: Context and Coprocessor Into Processing/acquistion Loopmentioning

confidence: 99%

Section: Example Of Achievable Performancementioning

confidence: 99%

See 1 more Smart Citation

Smart Camera Based on Embedded HW/SW Coprocessor

Mosqueron¹,

Dubois²,

Mattavelli³

et al. 2008

EURASIP Journal on Embedded Systems

View full text Add to dashboard Cite

show abstract

“…To face the high data flow induced by computer vision algorithms, an alternative approach consists of performing some image processing on the sensor focal plane. Hence, to achieve some simple low-level image processing tasks (early-vision), a smart sensor integrates analog and/or digital processing circuits in the pixel [4][5][6] or at the edge of the pixels array [7]. The integration of pixels array and image processing circuits on a single monolithic chip makes the system more compact and allows the behaviour and the response of the sensor to be enhanced.…”

Section: Introductionmentioning

confidence: 99%

A smart sensor-based vision system: implementation and evaluation

Elouardi¹,

Bouaziz²,

Dupret³

et al. 2006

J. Phys. D: Appl. Phys.

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These days, smart home applications such as concierge service for residents, home appliance control, and so on are attracting attention. To realize these applications, we need a system which recognizes various human activities accurately with a low cost device. There are many studies on the activity recognition in a smart home. We also have proposed an activity recognition technique in a smart home by utilizing digital-output-PIR (passive infrared) sensors, door sensors, and power meters. However, the study has an unsolved issue: we cannot distinguish similar activities happening at the same place, for example, "eating" and "reading" while sitting on a sofa. In order to cope with this challenge, we introduce ALPAS: analog-output-PIR-sensor-based activity recognition technique which recognizes the different activities in the same place. Our technique recognizes user's activity by utilizing machine learning with frequency components of the sensor's output as features. However, because the number of features used in ALPAS is 1000 for each analog PIR-sensor, a large capacity memory is required. To reduce the number of features, we select a part of the sensing data. We call the starting point of the selected data as starting frequency (SF) and ending part as ending frequency (EF). We searched SF and EF using a grid search, and evaluated the recognition accuracy. We evaluated the proposed technique in a smarthome testbed. In the evaluation, five participants performed four different activities while sitting on a sofa. As a result, we achieved F-Measure: 63.9% when the EF is 1.4 Hz, and F-Measure: 50% or lower when the SF is 9.9 Hz or higher.

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CMOS imager design for fast centroid readout

Thomas

Hornsey

Yip

Canadian Conference on Electrical and Computer Engineering 2004 (IEEE Cat. No.04CH37513)

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Numerous applications of imaging systems involve the defemination ofthe centroid location of a localized region of high intensify (a "spot'7 that is easily distinguished from the background. The goal of the present work was to tailor the design of a custom CMOS imager to facilitate the centroid-location task. On-pixel circuity, readout methods, on-chip post-readout processing and other factors were considered in the design process. The 'design process' included system modeling, simulation and experimental validation as well as chip-level design.A triangulation rangefinder instrument was constructed to evaluate imager alternatives.The precision of the range determination is proportional to the precision of the location of the centroid of the image of an optical spot.Range measurements are presented to demonstrate that uncertainfy in centroid position, the dominant error source, can be significantly reduced by averaging. A novel CMOS imager design concept is described Using on-chip processing and a bixel-binav: rowkolumnparallel readout scheme, range values are expected to have an update rate as high as 1 MHz. Key aspects of the chip design are evaluated, especially as they pertain to update rate and the use of on-chip averaging to enhance precision.

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Pixel-parallel CMOS active pixel sensor for fast object location

Cited by 6 publications

References 5 publications

Smart Camera Based on Embedded HW/SW Coprocessor

Smart Camera Based on Embedded HW/SW Coprocessor

A smart sensor-based vision system: implementation and evaluation

CMOS imager design for fast centroid readout

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