PL-NPU: An Energy-Efficient Edge-Device DNN Training Processor With Posit-Based Logarithm-Domain Computing

Wang, Yang; Deng, Dazheng; Liu, Leibo; Wei, Shaojun; Yin, Shouyi

doi:10.1109/tcsi.2022.3184115

Cited by 7 publications

(2 citation statements)

References 31 publications

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“…Although posit arithmetic was designed to have similar circuitry to the floating-point format, the variable length of the fields and the signed hidden bit of the fraction requires redesigning some of the logic when implementing posit operators. However, such an effort might be compensated by the benefits of using posit arithmetic-its higher accuracy, when compared with standard floating-point, can reduce the bitwidth of the data and operations of scientific computations without sacrificing the accuracy of the results, with all the benefits this entails at the hardware level [25].…”

Section: A Posit Notationmentioning

confidence: 99%

Generating Posit-Based Accelerators With High-Level Synthesis

Murillo

Barrio

Botella

et al. 2023

IEEE Trans. Circuits Syst. I

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Recently, the posit number system has demonstrated a higher accuracy over standard floating-point arithmetic for many scientific applications. However, when it comes to implementing accelerators for these applications, the tool support for this arithmetic format is still missing, especially during the high-level synthesis (HLS) step. In this paper, we incorporate the posit data type into the high-level synthesis (HLS) design process, so that we can generate the register-transfer level (RTL) implementation directly from a given behavioral specification, but using posit numbers instead of the classical floating-point notations. Our evaluations show that, even if posit-based circuits require more area than their floating-point counterparts, they offer higher accuracy when using the same bitwidth. For example, using posit arithmetic can reduce computation errors by about two orders of magnitude when compared to using standard floating-point numbers. Our approach also includes an alternative to mitigate the high overheads of the posits and broadening the potential use of this format. We also propose a hybrid scheme that uses posit numbers only in the private local memory, while the accelerator operates in the classic floatingpoint notation. This solution is useful when the designers want to optimize local memories and data transfers, but still use legacy HLS tools that only support traditional floating-point notations.

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Section: A Posit Notationmentioning

confidence: 99%

Generating Posit-Based Accelerators With High-Level Synthesis

Murillo

Barrio

Botella

et al. 2023

IEEE Trans. Circuits Syst. I

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“…Many fields have benefited from the posit data format since its emergence, including weather forecasts [4], graph processing [5] and deep learning [6]. For deep learning applications, in particular, prior arts have optimized deep neural networks (DNNs) using posit data types for efficient inference [7] [8] and training [9] [10].…”

Section: Introductionmentioning

confidence: 99%

PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications

Li¹,

Fang²,

Wang³

2023

Preprint

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Posit has been a promising alternative to the IEEE-754 floating point format for deep learning applications due to its better trade-off between dynamic range and accuracy. However, hardware implementation of posit arithmetic requires further exploration, especially for the dot-product operations dominated in deep neural networks (DNNs). It has been implemented by either the combination of multipliers and an adder tree or cascaded fused multiply-add units, leading to poor computational efficiency and excessive hardware overhead. To address this issue, we propose an open-source posit dot-product unit, namely PDPU, that facilitates resource-efficient and high-throughput dotproduct hardware implementation. PDPU not only features the fused and mixed-precision architecture that eliminates redundant latency and hardware resources, but also has a fine-grained 6-stage pipeline, improving computational efficiency. A configurable PDPU generator is further developed to meet the diverse needs of various DNNs for computational accuracy. Experimental results evaluated under the 28nm CMOS process show that PDPU reduces area, latency, and power by up to 43%, 64%, and 70%, respectively, compared to the existing implementations. Hence, PDPU has great potential as the computing core of posit-based accelerators for deep learning applications.

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