PLAC: Piecewise Linear Approximation Computation for All Nonlinear Unary Functions

Dong, Hongxi; Wang, Manzhen; Luo, Yuanyong; Zheng, Muhan; An, Mengyu; Ha, Yajun; Pan, Hongbing

doi:10.1109/tvlsi.2020.3004602

Cited by 49 publications

(29 citation statements)

References 27 publications

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“…However, the calculation of the exhaustion method is time consuming, resulting in the segmenter running on the software for hours or even days. Therefore, we optimize the calculation process of the segmenter based on the method proposed in [9].…”

Section: Minimization Of the Segments Number With A Given Precisionmentioning

confidence: 99%

“…In order to solve the problem of too high a delay in the above indexing method, this paper proposes a new indexing method based on [8,9], as shown in the left side of Figure 7. For a function with n segments, the input is simultaneously compared with the starting points S 2 , S 3 , .…”

Section: Test Of Segmenter Performancementioning

confidence: 99%

“…This method can be further subdivided into linear approximation and quadratic approximation depending on the polynomial approximation degree. Linear approximation has advantages when the accuracy is low, because of its high speed and low computation complexity [8,9]. It is usually used in low-precision applications or to provide an initial value for other methods.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Piecewise Parabolic Approximate Computation Based on an Error-Flattened Segmenter and a Novel Quantizer

Luo

Zheng

et al. 2021

Electronics

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This paper proposes a novel Piecewise Parabolic Approximate Computation method for hardware function evaluation, which mainly incorporates an error-flattened segmenter and an implementation quantizer. Under a required software maximum absolute error (MAE), the segmenter adaptively selects a minimum number of parabolas to approximate the objective function. By completely imitating the circuit’s behavior before actual implementation, the quantizer calculates the minimum quantization bit width to ensure a non-redundant fixed-point hardware architecture with an MAE of 1 unit of least precision (ulp), eliminating the iterative design time for the circuits. The method causes the number of segments to reach the theoretical limit, and has great advantages in the number of segments and the size of the look-up table (LUT). To prove the superiority of the proposed method, six common functions were implemented by the proposed method under TSMC-90 nm technology. Compared to the state-of-the-art piecewise quadratic approximation methods, the proposed method has advantages in the area with roughly the same delay. Furthermore, a unified function-evaluation unit was also implemented under TSMC-90 nm technology.

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Section: Minimization Of the Segments Number With A Given Precisionmentioning

confidence: 99%

Section: Test Of Segmenter Performancementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Piecewise Parabolic Approximate Computation Based on an Error-Flattened Segmenter and a Novel Quantizer

Luo

Zheng

et al. 2021

Electronics

Self Cite

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show abstract

“…In this case, hardware implementation is based on several parallel comparators, single multiply addition, and storage of slope, intercept, and endpoints for each segment. In [38], with 15 segments, a mean approximation error of 1.2 × 10 −4 is achieved to satisfy the 12-bit fractional fixed-point format. However, the available representation in the current design has an 8bit fractional length that corresponds to 3.9 × 10 −3 level accuracy.…”

Section: Logarithm Compressionmentioning

confidence: 99%

Drone Detection Sensor With Continuous 2.4 GHz ISM Band Coverage Based on Cost-Effective SDR Platform

Flak

2021

IEEE Access

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The development of Unmanned Aerial Vehicles (UAVs), commonly referred to as drones, has introduced revolutionary changes in many areas over the past few years. However, aside from opening new possibilities, the usage of drones in an irresponsible and dangerous manner leads to many hazardous incidents. This paper presents a drone detection sensor with a continuous 2.400 GHz-2.483 GHz operational frequency range for detection methods based on passive radio frequency imaging techniques. The implementation based on Software Defined Radio (SDR) and Field Programmable Logic Array (FPGA) hardware that overcomes the 40 MHz real-time bandwidth limit of other popular SDRs is presented utilizing low-cost off-the-shelf components. Furthermore, hardware realization of the signal processing chain for specific detection algorithms is proposed to minimize the throughput between SDR and the companion computer and offload software computations. The device validation is made in a laboratory and real-life scenario and presented in relation to the sensor used in other works. The measurements indicate some detection sensitivity reduction compared to the reference receiver, consistent with hardware specifications. The final analysis demonstrates the proposed device's relevance as a sensor for obtaining machine learning datasets and as a part of a final anti-drone system.

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“…However, recent applications of ANNs, e.g., IoT, medical systems, and telecommunication, require platforms with high throughput and the capacity to execute the algorithms in real-time. An attractive solution is the development of hardware neuronal networks (HNN) in Field-Programmable Gate Arrays (FPGAs) [15][16][17][18][19][20][21]. In this regard, the FPGA-based implementation of AFs in HNN is one of the challenges for embedded system design according to recent studies; this is because the AF implementations require low hardware resources and low power consumption [1,2,5,12,[22][23][24][25].…”

Section: Introductionmentioning

confidence: 99%

Hardware-Based Activation Function-Core for Neural Network Implementations

et al. 2021

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Today, embedded systems (ES) tend towards miniaturization and the carrying out of complex tasks in applications such as the Internet of Things, medical systems, telecommunications, among others. Currently, ES structures based on artificial intelligence using hardware neural networks (HNNs) are becoming more common. In the design of HNN, the activation function (AF) requires special attention due to its impact on the HNN performance. Therefore, implementing activation functions (AFs) with good performance, low power consumption, and reduced hardware resources is critical for HNNs. In light of this, this paper presents a hardware-based activation function-core (AFC) to implement an HNN. In addition, this work shows a design framework for the AFC that applies a piecewise polynomial approximation (PPA) technique. The designed AFC has a reconfigurable architecture with a wordlength-efficient decoder, i.e., reduced hardware resources are used to satisfy the desired accuracy. Experimental results show a better performance of the proposed AFC in terms of hardware resources and power consumption when it is compared with state of the art implementations. Finally, two case studies were implemented to corroborate the AFC performance in widely used ANN applications.

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PLAC: Piecewise Linear Approximation Computation for All Nonlinear Unary Functions

Cited by 49 publications

References 27 publications

Piecewise Parabolic Approximate Computation Based on an Error-Flattened Segmenter and a Novel Quantizer

Piecewise Parabolic Approximate Computation Based on an Error-Flattened Segmenter and a Novel Quantizer

Drone Detection Sensor With Continuous 2.4 GHz ISM Band Coverage Based on Cost-Effective SDR Platform

Hardware-Based Activation Function-Core for Neural Network Implementations

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