Placement and Timing for FPGAs Considering Variations

Statistical Generic and Chip-Specific Skew Assignment for Improving Timing Yield of FPGAs

“…For instance, if a chip has a critical path delay that exceeds the specification by 1.4%, it is placed in the [1,2) delay bin meaning that the clock period of the chip exceeds timing specification by 1-2%. From the figure we can see that most of the failing chips fall in the bins (0,1] and (1,2]. Furthermore, about 88% of failed chips fall in the extended delay bin (0,5].…”

“…In this work we use deterministic place and route algorithms since our objective is to study the effectiveness of the skew assignment technique. However, skew assignment can be used in conjunction with statistical place and route algorithms ( [1], [3]) to augment the timing yield further and to meet more aggressive timing specifications. Using SSTA, we set the values of T fast ,T medium and T slow such that fast, medium and slow bins contain 40%,30% and 29.9% of the chips respectively [1].…”

“…However, skew assignment can be used in conjunction with statistical place and route algorithms ( [1], [3]) to augment the timing yield further and to meet more aggressive timing specifications. Using SSTA, we set the values of T fast ,T medium and T slow such that fast, medium and slow bins contain 40%,30% and 29.9% of the chips respectively [1]. We then perform Monte Carlo simulations with 10,000 samples to gather statistics regarding the number of chips in each bin both with and without skew assignment.…”

“…To alleviate the problems due to variability, statistical optimization techniques have been adopted for a long time by ASIC designers. Recently the FPGA community has also started to take note of the potential pitfalls associated with not considering process variations in the design phase( [1], [2], [3]). Statistical static timing analysis has been widely used to account for variations and to produce tighter delay distributions to improve timing yield.…”

Statistical Dual-Vdd Assignment for FPGA Interconnect Power Reduction

“…Similar to ASICs, FPGAs are subject to variations in the operation of transistors comprising the logic functionality and the switching muxes. Unique in FPGAs, the guard-banded timing model will be applied to designs unknown in advance, and can be arbitrarily conservative or aggressive [1]. Statistical analysis on timing or power is necessary under the presence of variations.…”