Placement-driven partitioning for congestion mitigation in monolithic 3D IC designs

Abstract

Monolithic 3D is an emerging technology that enables integration density which is orders of magnitude higher than that offered by through-silicon-vias (TSV). In this paper we demonstrate that a modified 2D placement technique, coupled with a post-placement partitioning step, is sufficient to produce high quality monolithic 3D placement solutions. We also present a commercial router based monolithic inter-tier via (MIV) insertion methodology that dramatically improves the routability of monolithic 3D-ICs. We develop a routing demand model for monolithic 3D-ICs, and use it to develop an O(N ) min-overflow partitioner that enhances routability by off-loading demand from one tier to another. This technique reduces the routed wirelength and the power delay product (PDP) by up to 4% and 4.33% respectively, under the same half-perimeter wirelength. This allows a two-tier monolithic 3D-IC to achieve, on average, 19.2% and 12.1% improvement in routed wirelength and PDP over 2D, even with reduced metal layer usage.

3DIC benefit estimation and implementation guidance from 2DIC implementation

“…The following subsections summarize (i) related literature; (ii) our baseline 2D and 3D implementation flows, which replicate the flows of [15] [16]; and (iii) a new, tight upper bound on potential wirelength reduction in 3DIC that can inform design-space exploration.…”

“…Another 3DIC implementation flow addresses design requirements for sequential 3D [2] technology that permits cell-level 3D integration. Panth et al [15] [16] propose a design flow for sequential 3D based on commercial EDA and in-house tools, and validate the flow on OpenSPARC T2 and other IPs [23]. This latter flow is, we believe, the most sophisticated and full-featured in the research literature; we have transplanted and used this flow in our present work.…”

“…As mentioned above, the 3DIC implementation flows of [15] [16] are currently published in the research literature. To develop our 3D power estimation model, we use the Shrunk2D (S2D) and 3D flows from [16] as proxies for golden 3DIC implementation.…”

“…• Of independent interest is a tight bound on the wirelength benefit of 3D integration vs. 2D integration (Section 2.3), which informs our use of WLM scaling in our modeling flow. Also of independent interest is our observation (Section 2.2) of qualitatively different 3DIC benefit results for the well-studied OpenSPARC T2 design [24], after improving the enablement of experiments starting from the 3D implementation flow of [15].…”

Design challenges and solutions for ultra-high-density monolithic 3D ICs

“…In this design style, existing 2D standard cells are placed onto a 3D space [6], [3], [7]. The advantage of this design style is that it offers reuse of existing standard cells, a 50% or more footprint area reduction, and since each tier has equal number of metal layers as 2D designs, no increase in pin density.…”