Planarized, Extendible, Multilayer Fabrication Process for Superconducting Electronics

Abstract

We report on technique and results for superconductor electronics fabrication process, featuring customizable number of planarized superconducting layers. The novel technique enhanced yield on stackable vias of our standard planarized process (RIPPLE) by eliminating the need for an additional deposition of aluminum as an etch stop in the metal-via stack. The drawback of the previous approach was the difficulty in processing aluminum using either wet or dry etch mechanisms. Here, we discuss details of the novel fabrication process flow and its realization for 4.5 kA/cm 2 fabrication process with six Nb layers with two fully planarized layers. We report test results of various planarization diagnostics structures, accounting the influence of topology on Josephson junction quality, as well as yield and critical current of via stacks. We also report on inductance measurement results providing information on interlayer dielectric thickness for planarized layers; confirming a good uniformity over the wafer. Basic components of superconducting logic such as dc/SFQ, SFQ/dc converters, Josephson transmission lines (JTLs), and simple digital circuits such as half-adder (HA) have been designed, fabricated and tested using either conventional (RSFQ) or energy-efficient (ERSFQ) approach. The ERSFQ HA cells with bias inductors fabricated in two planarized layers were shown to function with the operational margins of +/−22%.

A Review of X-ray Microcalorimeters Based on Superconducting Transition Edge Sensors for Astrophysics and Particle Physics

“…The state-of-the-art system of wiring lines consists of multiple broad-side coupled lines, embedded within oxide layers by applying chemical mechanical polishing so that planarized microstripline layers can be stacked in a vertical direction. Massachusetts Institute of Technology Lincoln Laboratory has demonstrated the process with six superconducting Nb layers for superconducting electronics [98][99][100]. Microphotograph of an Au X-ray absorber.…”

SMART: A Heterogeneous Scratchpad Memory Architecture for Superconductor SFQ-based Systolic CNN Accelerators

“…We ran the superconductor SPICE simulator, JoSIM [7], to validate the results of pipelined CMOS-SFQ arrays generated by our modified cryo-mem. We assumed Hypres ERSFQ 1.0𝜇𝑚 technology [56] to validate the splitter unit. Figure 13(a) exhibits the latency comparison of a splitter unit with various PTL lengths between our model and JoSIM, while their energy correlation is described in Figure 13(b).…”

Lynx x-ray microcalorimeter

“…A promising multilayer Nb process has been under development by a few places, such as Hypres and Massachusetts Institute of Technology Lincoln Laboratory (MIT/LL). [26][27][28] MIT/ LL recently developed a process that supports eight superconducting Nb metal layers for superconducting electronics. It utilizes extreme UV (EUV) lithography to achieve submicron line/space resolution and chemical mechanical polishing (CMP) to ensure all metal layers are deposited on a surface with topography height of less than 40 nm.…”