Plasma-Assisted Dry Etching of Ferroelectric Capacitor Modules and Application to a 32M Ferroelectric Random Access Memory Devices with Submicron Feature Sizes

Abstract

In the manufacturing of a 32M ferroelectric random access memory (FRAM) device on the basis of 0.25 design rule (D/R), one of the most difficult processes is to pattern a submicron capacitor module while retaining good ferroelectric properties. In this paper, we report the ferroelectric property of patterned submicron capacitor modules with a stack height of 380 nm, where the 100 nm-thick Pb(Zr, Ti)O 3 (PZT) films were prepared by the sol-gel method. After patterning, overall sidewall slope was approximately 70 • and cell-to-cell node separation was made to be 80 nm to prevent possible twin-bit failure in the device. Finally, several heat treatment conditions were investigated to retain the ferroelectric property of the patterned capacitor. It was found that rapid thermal processing (RTP) treatment yields better properties than conventional furnace annealing. This result is directly related to the near-surface chemistry of the PZT films, as confirmed by X-ray photoelectron spectroscopy (XPS) analysis. The resultant switching polarization value of the submicron capacitor was approximately 30 µC/cm 2 measured at 3 V.

Chemistry of surface nanostructures in lead precursor-rich PbZr0.52Ti0.48O3 sol–gel films

“…At first sight it is therefore surprising that a Zr rich surface oxide shows a distinct core level binding energy with respect to that of Zr in PZT. However, the XPS data in the literature shows that the Zr binding energy is (181.4 ±0.1) eV in PZT [10,24,35,32,36,37,38,39,40,41,42,43,44,45,46] and (182.4 ±0.3) eV in ZrO 2 [47,48,49,50,51,52,53,54,55,56], in excellent agreement with the 1 eV shift measured here. Beyond the immediate chemical environment of the Zr emitter, two other effects may influence the BE shift.…”

The memory characteristics of submicron feature-size PZT capacitors with PtOxtop electrode by using dry-etching

“…one mask per dry etching process, to reduce the cell area [14]. Otherwise, it becomes difficult to obtain high anisotropy during capacitor stack etching without process degradation because the capacitor node-to-node space must also be shrunk down by decreasing the device size [15].…”