Plasma charge-induced corrosion of tungsten-plug vias in CMOS devices

bit failure as shown in Fig. 1(b) which shows failure bit map In this paper, systematic pair bit failure is analyzed in failure of center die. bit map of deep-submicron CMOS technology. Tungsten plug corrosion in contacts of stacked contact/metal/via structure is observed from careful analysis of failure bit. Then, some experiments have been carried out to identify and g X resolve this corrosion failure. This corrosion reaction occurred through the void space, which is formed by excess via over-etch along the sidewall of underlying metal in contact-metal-via stack structure and by the plasma charging and electrochemical reaction during via etch and post cleaning. This failure can be practically avoided by optimizing via over-etch time and underlying metal profile | and it is confirmed by product yield and failure bit map data.

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Light enhanced tungsten via corrosion

Westergard

Belisle

Florence

et al.

IEEE International Integrated Reliability Workshop Final Report, 2002.

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Plasma charge-induced corrosion of tungsten-plug vias in CMOS devices

Cited by 4 publications

References 2 publications

Failure rate and yield-limiting tungsten plug corrosion diagnosis using characterization test vehicles

Failure rate and yield-limiting tungsten plug corrosion diagnosis using characterization test vehicles

New Failure Analysis of Tungsten Plug Corrosion in Via Process

Light enhanced tungsten via corrosion

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