Plasma Deposition and Development of Ultralow-k Bilayer SiCN<sub>x</sub>/SiCN<sub>y</sub> Dielectric Cu Cap for 32 nm CMOS Devices

Nguyen, S.; Grill, A.; Cohen, S.; Shobha, H.; Klymko, N.; Simonyi, E.; Haigh, T.; Hu, Chenming; Adams, Edward N.; Liniger, E.; Madan, A.; Shaw, T. M.; Ryan, E. Todd; Cheng, Tien; Herman, Joshua; Young, Robert M.

doi:10.1149/ma2009-02/26/2159

Cited by 4 publications

(6 citation statements)

References 0 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The dielectrics of SiN, SiNO, SiCN, SiCOH, pSiCOH for pinch off deposition were deposited in a commercial high throughput production-worthy 13.6 MHz RF 300 mm Plasma Chemical Vapor Deposition process (PECVD) system at 350 C. The dielectrics were deposited using a combination of various silane (SiH4) or carbosilane or organosilicon precursors with other reactant gases such as Ammonia ((NH 3 ), Nitrogen (N 2 ), Oxygen (O 2 ), or Nitrous Oxide (N 2 O) as described in previous publications. [12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29] The advanced highly robust conformal SiN 6 was deposited by cyclic processing using Silane, Ammonia and Nitrogen. The SiCN dielectric was also deposited at 350 C using a combination of Trimethyl Silane (TMS) + Ammonia (NH 3 ) and (optionally) with Hydrogen for robust SiCN film.…”

Section: Experiment-film Deposition and Pinch Off Processmentioning

confidence: 99%

“…21,22 Table I summarizes various plasma deposited dielectric films and their properties. These dielectric films have been developed and used by our laboratories and have appeared in many of our publications [12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29] over the years. Since similar materials can be deposited under various conditions and have different properties, our reference publications [12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29] is to prefer to specific process chemistry and tooling that use for this pinch off deposition processes.…”

Section: Experiment-film Deposition and Pinch Off Processmentioning

confidence: 99%

See 1 more Smart Citation

Pinch Off Plasma CVD Deposition Process and Material Technology for Nano-Device Air Gap/Spacer Formation

Nguyen¹,

Haigh²,

Cheng³

et al. 2018

ECS J. Solid State Sci. Technol.

View full text Add to dashboard Cite

As integrated circuits for high performance CMOS devices scale down to < = 10 nm dimension, further reductions in capacitance are vitally important for device performance. It is important to reduce capacitance in the FEOL and BEOL device structures while maintaining fabrication integration robustness. This paper presents an overview of material and process technology requirements for FEOL air spacer and BEOL air gap formation using a pinch off deposition approach. These approaches utilize established dielectric materials and processes such as Plasma CVD of SiN, SiCN, SiCOH, pSiCOH, in the formation of the air spacer/air gap. The selection of these dielectric materials and processes has a large impact in the void (gap) dimension and volume. The void dimension and volume in airgap/air spacer structures can be controlled with various dielectric deposition processes and materials to facilitate subsequent process fabrication steps, and ultimately to build a robust device with substantial capacitance reduction.

show abstract

Section: Experiment-film Deposition and Pinch Off Processmentioning

confidence: 99%

Section: Experiment-film Deposition and Pinch Off Processmentioning

confidence: 99%

Pinch Off Plasma CVD Deposition Process and Material Technology for Nano-Device Air Gap/Spacer Formation

Nguyen¹,

Haigh²,

Cheng³

et al. 2018

ECS J. Solid State Sci. Technol.

View full text Add to dashboard Cite

show abstract

“…Plasma-enhanced chemical vapor deposited (PECVD) low-k silicon carbon nitride (SiCNH) has become the predominant dielectric Cu-diffusion cap layer chosen by the industry. The development and integration of various low-k Cu cap layers for 45/32 nm CMOS back end of line (BEOL) has been previously reported by our group [5][6][7][8] reactive plasma ambient. In case of pSiCOH dielectrics, the cap structures may also later be exposed to additional high UV cure steps at 350-400 o C. These processes are repeated many times during subsequent device fabrication steps.…”

Section: Introductionmentioning

confidence: 99%

“…As the devices are exposed to high temperature and harsh plasma oxidation environment (oxygen based PECVD SiCOH deposition), the thin cap must remain as a robust Cu oxidation and Cu-diffusion barrier to maintain device's yield, reliability and performance. A thick (25-40 nm) SiCNH cap and bilayer SiCN x H/SiCN y H caps have been optimized for 32-90 nm CMOS BEOL devices [6][7][8]. For sub-20 nm devices, the thickness of the cap needs to be scaled down to minimize the overall device's capacitance.…”

Section: Introductionmentioning

confidence: 99%

Ultrathin (8-14 nm) Conformal SiN for sub-20 nm Copper/Low-k Interconnects

et al. 2014

View full text Add to dashboard Cite

A multilayer SiN barrier film with high breakdown field and low leakage current is developed for Cu low-k interconnects and is compared with the SiCNH barrier film used in previous technology nodes. Ultrathin SiN barrier cap films also provide high conformality and fill recessions in Cu lines as observed after CMP. The conformal ultrathin (8-14 nm) multilayer SiN cap is robust with higher breakdown field, lower leakage and forms a good oxidation barrier. The electromigration activation energy for a SiN cap layer of 10-12 nm dielectric thickness is about 0.9 eV.

show abstract

“…A conservative approach was proposed by Nguyen et al, 7 who prepared a dielectric barrier bilayer of dense SiN y /porous SiC x N y , exhibiting 12% porosity, by performing plasma deposition of dimethylsilacyclopentane and NH 3 and then using UV to cure the samples. The dense films of the bilayer on top helped protect the underlying copper layer against plasma-induced damage and oxidation caused by the diffusion of oxygen, whereas the bottom porous film of the bilayer contributed to a reduction in the dielectric constant.…”

mentioning

confidence: 99%

Effect of Porogen Incorporation on Pore Morphology of Low-k SiC_xN_yFilms Prepared Using PECVD

Jeng

et al. 2014

ECS J. Solid State Sci. Technol.

View full text Add to dashboard Cite

Low-k porous SiC x N y films were prepared through plasma-enhanced chemical vapor deposition, using 1,3,5-trimethyl-1,3,5-trivinylcyclotrisilazane (VSZ) as the matrix precursor and epoxycyclohexane (ECH) as a porogen. The effects of porogen loading and deposition temperature on porogen incorporation, pore morphology, and the properties of porous SiC x N y films were examined. In addition, the impact of film shrinkage and the corresponding nanopore structures after annealing were studied. The porosity of films deposited at 100 • C increased from 1.8% to 19.8% when ECH loading increased to 30%, above which the porosity remained nearly constant because of high film shrinkage. The pore size decreased slightly from 4.1 to 3.7 nm when ECH loading increased to 30%, above which the pores became larger and were broadly distributed. By contrast, increasing deposition temperature at 20% ECH loading decreased porogen incorporation and increased film density. The porosities and pore size of films decreased, respectively, when the deposition temperature increased. A short-range ordering of pores was observed only at low deposition temperatures because the N-Si-C cross-linked structures and organic phase were present. Optimized processing parameters facilitated the fabrication of low-k porous SiC x N y films exhibiting 19.8% porosity, 3.7-nm pores, a k value of 3.18, and an elastic modulus of 7. In CMOS backend interconnections, low-k etch-stop/dielectric barrier materials such as silicon carbonitride (SiC x N y ) (k = 4.5-5.5) and ultralow-dielectric-constant (ultralow-k, ULK) inter-layer dielectrics (ILDs) have been used to lower the effective capacitance (k eff ) in the 45 and 32 nm node and beyond.1 Silicon carbonitride films are typically prepared by performing plasma-enhanced chemical vapor deposition (PECVD) of multi-precursors such as silane/ammonia (or nitrogen)/methane 2,3 and trimethylsilane/amonia. 4 Recently, single source precursors such as hexamethyldisilazane 5 and BASICN 6 have been used for preparing dense low-k SiC x N y films by using PECVD because these films display low defects (i.e., low leakage current) and higher etch selectivity due to high C/Si ratio. 6 To further reduce the dielectric constant of silicon carbonitride film, incorporation of porosity is one of the primary approaches, in addition to continued addition of elements with lower polarizability such as more C atoms.A conservative approach was proposed by Nguyen et al., 7 who prepared a dielectric barrier bilayer of dense SiN y /porous SiC x N y , exhibiting 12% porosity, by performing plasma deposition of dimethylsilacyclopentane and NH 3 and then using UV to cure the samples. The dense films of the bilayer on top helped protect the underlying copper layer against plasma-induced damage and oxidation caused by the diffusion of oxygen, whereas the bottom porous film of the bilayer contributed to a reduction in the dielectric constant.8 Because they possess a bilayer (dense film/porous film) or sandwich (dense film/porous film/dense film) ...

show abstract

Plasma Deposition and Development of Ultralow-k Bilayer SiCN_x/SiCN_y Dielectric Cu Cap for 32 nm CMOS Devices

Abstract: not Available.

Cited by 4 publications

References 0 publications

Pinch Off Plasma CVD Deposition Process and Material Technology for Nano-Device Air Gap/Spacer Formation

Pinch Off Plasma CVD Deposition Process and Material Technology for Nano-Device Air Gap/Spacer Formation

Ultrathin (8-14 nm) Conformal SiN for sub-20 nm Copper/Low-k Interconnects

Effect of Porogen Incorporation on Pore Morphology of Low-k SiC_xN_yFilms Prepared Using PECVD

Contact Info

Product

Resources

About

Plasma Deposition and Development of Ultralow-k Bilayer SiCNx/SiCNy Dielectric Cu Cap for 32 nm CMOS Devices

Abstract: not Available.

Cited by 4 publications

References 0 publications

Pinch Off Plasma CVD Deposition Process and Material Technology for Nano-Device Air Gap/Spacer Formation

Pinch Off Plasma CVD Deposition Process and Material Technology for Nano-Device Air Gap/Spacer Formation

Ultrathin (8-14 nm) Conformal SiN for sub-20 nm Copper/Low-k Interconnects

Effect of Porogen Incorporation on Pore Morphology of Low-k SiCxNyFilms Prepared Using PECVD

Contact Info

Product

Resources

About

Plasma Deposition and Development of Ultralow-k Bilayer SiCN_x/SiCN_y Dielectric Cu Cap for 32 nm CMOS Devices

Effect of Porogen Incorporation on Pore Morphology of Low-k SiC_xN_yFilms Prepared Using PECVD