This article demonstrates full self-aligned invertedstaggered amorphous silicon thin-film transistors (TFT's) fabricated using selective plasma deposition of doped microcrystalline silicon source/drain contacts. Back-side exposure, using the bottom metal gate as the mask, produced the self-aligned contact openings. Selective deposition of the n+ silicon contact layer assures self-aligned low resistance contacts and eliminates the need for reactive ion etching of the n+ silicon. Complete TFT fabrication requires no critical alignment steps. Transistors have linear mobility between 0.6 and 1.1 cm 2 /Vs, threshold voltage of 3.0 V, and sub-threshold slope of 0.35 V/decade. The OFF current is <10 011 A with 010 V gate voltage and 10 V between the source and drain, and ON/OFF ratios exceed 10 6 . T HE demand for active matrix liquid crystal displays (AMLCD's) is expected to grow, with more emphasis on technologies to simplify manufacturing and produce high-performance devices. Inverse-staggered amorphous silicon thin-film transistors (TFT's) are the most widely used switching devices in AMLCD arrays [1] because they have acceptable drive capability, excellent off-state current, and can be reliably processed.Improved drive current and reduced parasitic capacitance in a-Si:H TFT's will enable higher resolution and larger screen sizes, minimize image flicker and sticking, and improve the gray level uniformity. High drive currents will also be important for other TFT driven applications, including activematrix organic LED displays. Enhanced drive current can be achieved by improving the mobility of the silicon layer, and/or by reducing the channel resistance, for instance, by reducing the channel length. Parasitic capacitance, on the other hand, can be minimized by reducing the gate-source overlap, which can be done by self-aligned processes. The limiting issues for fabrication of short-channel inverse-staggered TFT's are:1) the constraints of pattern overlay requirements and alignment accuracy when forming the source/drain contacts; and 2) controlled etching of n Si from between the source and drain. . Publisher Item Identifier S 0741-3106(98)04179-2.Self-alignment approaches including back-side exposure [2] have been used to simplify contact positioning and reduce the mask count. Self-aligned devices, where contacts are positioned and formed without overlay, alignment, or n etching requirements, have also been demonstrated using ionshower doping [3], and laser contact doping [4]. The ionshower doping method can result in contact damage, and the laser approach adds the complexity of the laser process. In this article, we present an alternate approach, based on widely used parallel-plate rf PECVD, to fabricate contacts using selective area deposition of self-aligned doped microcrystalline silicon ( c-Si) [5]. Selective deposition has been applied previously to top-gate TFT's [6], where selective deposition of n silicon on metal was used to form the contacts. To use selective deposition in an inverse-staggered TFT, however...