Plasma processing of III-V materials for energy efficient electronics applications

Abstract

This paper reviews some recent activity at the James Watt Nanofabrication Centre in the University of Glasgow in the area of plasma processing for energy efficient compound semiconductor-based transistors. Atomic layer etching suitable for controllable recess etching in GaN power transistors will be discussed. In addition, plasma based surface passivation techniques will be reviewed for a variety of compound semiconductor materials ( (100) and (110) oriented InGaAs and InGaSb).

Study of an Al2O3/GaN Interface for Normally Off MOS-Channel High-Electron-Mobility Transistors Using XPS Characterization: The Impact of Wet Surface Treatment on Threshold Voltage VTH

“…It has already been reported that stronger bombardment damage in the chlorine-based dry-etching process can make the V TH more negative . Therefore, we can expect a higher threshold voltage for an MOSc-HEMT processed without etching or with minimized etching-induced damage, e.g., lower bombardement, follow-up N 2 O oxidation treatment, neutral beam etching, or atomic layer etching. , An MOSc-HEMT processed without etching was recently reported using a regrown AlGaN/GaN heterostructure, with lower Ga oxidation and higher V TH than its etched recessed gate counterpart . Another way to increase the V TH would be the use of surface treatments able to “recover” etching-induced damage by providing enough nitrogen to eliminate the V N such as nitrogen-based plasma , or thermal treatments or to remove the damaged layer by wet treatment. , The study of interface properties of Al 2 O 3 /GaN samples by XPS can be helpful to choose the best gate-processing conditions for MOSc-HEMTs.…”

Recent Developments and Prospects of Fully Recessed MIS Gate Structures for GaN on Si Power Transistors

“…However, it has also been reported that UV photon damage in ALE was larger than in RIE owing to the longer plasma irradiation time [31]. It has been found that the ALE photon-induced damage can be mitigated by a post etch anneal process at temperatures which are compatible with the overall thermal budget of a GaN power transistor process flow [44].…”

“…The removal of the chlorinated layer has been investigated by the bombardment of Ar or He ions [35,36]. Several teams have reported on Cl 2 /Ar based ALE for GaN etching, achieving etch rates from 0.13 to 0.50 nm/cycle [35,36,44,[47][48][49][50] and surfaces as smooth as the as-grown sample. The presumed etching by-products are GaCl 3 (g) and N 2 (g) [49].…”

“…Cl 2 /Ar ALE parameters such as DC bias voltage during the Ar step, duration of each step, pressure during each step and gas ratio can be optimized in order to etch in the "ALE window" where there is no background etching during reaction A and only the modified layer by reaction A is removed by reaction B (no additional sputtering) [44,48,49]. A 2D fluid model is useful to determine the flux of reactive species, radicals and ions included, which arrive at the wafer surface.…”

“…An alternative to chlorination for the surface modification step is the use of a brominebased chemistry (HBr) that allows reduced Ar plasma power during the bombardment step [44].…”