Platform based design for a multimedia Motion JPEG decoder case study

Abstract

In recent years, computational requirements for embedded applications are increasing exponentially. This complexity, coupled with constantly evolving specifications, has forced designers to consider intrinsically flexible implementations. For this reason, heterogeneous multiprocessor architectural platforms are gaining prevalence for embedded systems. Deploying applications typical of multimedia domains is difficult, not only due to the heterogeneous parallelism in the platforms, but also due to the performance constraints that typify these systems. In this paradigm, the digital system-on-a-chip (SoC) platform-based design environment for shared memory multiple instructions multiple data (MIMD) architectures (Disydent) is used. The applicability of the Disydent design flow to systems in the multimedia domain is illustrated. The case studied consists in deploying a Motion JPEG decoder application onto a configurable prototype of a multiprocessor MIPS platform architecture.

ILP platform optimization of a YAPI parallel H.264/AVC encoder

“…Such a choice is not suitable for embedded systems that have strict power and cost constraints. An alternative solution is to use a multiprocessor approach to share the encoding execution time between several embedded processors [9]. For this, the sequential encoding C source code should be transformed into concurrent tasks communicating via dedicated communication mechanism.…”

DISYDENT evaluation for the design of multimedia systems

“…The case study consists of deploying a Motion JPEG decoder application onto the configurable prototype of the ASIM0 multiprocessor MIPS R3000 target platform [10]. The JPEG decoder is a multimedia application of medium complexity whose building blocks are used in many image and video processing algorithms [16]. For this study, the objective is to explore both modelling and mapping stages of the flow for an optimal implementation of the Motion JPEG decoder verifying constraints.…”

“…To achieve the required performance for real time operation, it is necessary to explore multiple ways of parallelization. Profiling the execution of the sequential application shall identify the major bottlenecks and the main subcomponents candidate for efficient parallelization [16]. The obtained profiling results are given in table 1.…”