POETS: Distributed Event-Based Computing – Scaling Behaviour

Abstract

POETS (Partially Ordered Event Triggered Systems) is a significantly different way of approaching large, compute intensive problems. The evolution of traditional computer technology has taken us from simple machines with tiny memory and (by todays standards) glacial clock speeds, to multi-gigabyte architectures running orders of magnitude faster, but with the same fundamental process at the heart: a central core doing one thing at a time. Over the past few years, architectures have appeared containing multiple cores, but exploiting these efficiently in the general case remains a ‘holy grail’ of computer science. POETS takes an alternative approach, made possible only today by the proliferation of cheap, small cores and massive reconfigurable platforms. Rather than program explicitly the behaviour of each core and each communication between them, as is done in conventional supercomputers, here the programmer defines a set of relatively small, simple behaviours for the set of cores, and leaves them to get on with it – with the right behavioural definitions, the system ‘self-organises’ to produce the desired results.

Synchronization in graph analysis algorithms on the Partially Ordered Event‐Triggered Systems many‐core architecture

“…Instead, processors consisting of larger numbers of far simpler cores, communicating by message-passing, can potentially achieve more performance from a single chip and scale more easily to large numbers of chips. This is the hypothesis of the POETS project (POETS [6,7]), which forms the wider context for the work described in this paper. On the project, researchers have constructed a prototype platform consisting of a 48-FPGA cluster and a many-core RISC-V overlay called Tinsel [37] programmed on top.…”

“…We explore these trade-offs using the Partially Ordered Event-Triggered Systems (POETS) platform [6,7]: a prototype hardware-software stack specifically suited for computing problems that can be decomposed into a large number of inter-communicating processes, and whose performance relies critically on communication efficiency. It provides a massivelyparallel multi-NoC hardware architecture comprised of a large number of small RISC-V cores [8] communicating via small (up to 64 bytes) packets.…”

An Alternate Feedback Mechanism for Tsetlin Machines on Parallel Architectures

“…POETS [6] (Partially Ordered Event Triggered Systems) is both a development-model and concrete hardware-software stack for developing parallel applications. An overview of the POETS architecture may be seen in Figure 1.…”

Macromolecular crowding is surprisingly unable to deform the structure of a model biomolecular condensate

“…Both the simulator and visualisation framework were inspired by a collaborative research project called POETS [58], which is an ongoing project exploring a new computing paradigm called event-triggered computing. In event-triggered computing, the applications and hardware are designed around the frequent exhange of events (small messages) between small asynchronous state machines, rather than the infrequent exchange of large messages between threads (as seen in MPI).…”