Point twin-bit RRAM in 3D interweaved cross-point array by Cu BEOL process

Chin, Y. L.; Chen, Shu-En; Hsieh, Ming‐Feng; Chang, Te‐Sheng; Lin, Chrong Jung; King, Ya‐Chin

doi:10.1109/iedm.2014.7046996

Cited by 8 publications

(5 citation statements)

References 6 publications

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“…Due to multilevel switching capability of SiO2-based ECM cells [58]- [60], the ON resistance can be typically tuned between 100 Ω to 1 MΩ and is almost independent of the device size [61]- [64]. These resistance values and the switching voltages are comparable to the performance reported for a number of VCM-and ECM-type devices [46], [65]- [67] fabricated by CMOS-and/or BEOL-compatible 27 nm to 90 nm technology nodes.…”

Section: Methodsmentioning

confidence: 55%

“…A disadvantage of some VCM-type devices is that their current/voltage behavior is considerably non-linear in the ON state. On contrast, the design requirements are exemplarily fulfilled for the ECM cell shown in Figure 1c, the nanoscale Cu-TaOx memristor reported by Chin et al [65] as well as the Ta/HfOx/Pd memristor reported by Li et al [47]. Table 1 gives an overview of some selected ECM-and VCM-type devices and their applicability for PMSCs.…”

Section: Methodsmentioning

confidence: 98%

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Programmable Mixed-Signal Circuits

Tappertzhofen

2023

Preprint

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A novel concept for programmable mixed-signal circuits is presented based on programmable transmission gates. For implementation, memristively switching devices are suggested as the most promising candidates for realization of fast and small-footprint signal routing switches with small resistance and capacity. As a proof-of-concept, LT Spice simulations of digital and analogue example circuits implemented by the new concept are demonstrated. It is discussed how important design parameters can be tuned in the circuity. Compared to competing technologies such as Field Programmable Analogue Arrays or Application-Specific Integrated Circuits, the presented concept allows for development of ultra-flexible, reconfigurable, and cheap embedded mixed-signal circuits for applications where only limited space is available or high bandwidth is required.

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Section: Methodsmentioning

confidence: 55%

Section: Methodsmentioning

confidence: 98%

Programmable Mixed-Signal Circuits

Tappertzhofen

2023

Preprint

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“…After several operations of changing its state, the RRAM still remains large read window in its read current level without window narrowing effect. Experimental data suggests that this point twin-bit RRAM can be operated within micro-second range [16]. The three different states of twin-bit RRAM in Fig.…”

Section: Switching Condition and DC Characteristicmentioning

confidence: 71%

“…5. The previous study [16] shows that the RRAM cell can be operated for over one hundred cycles and still maintain stable selection capability. Different forming directions do not affect the self-rectifying characteristic in LRS and the RRAM remains symmetric in HRS.…”

Section: Switching Condition and DC Characteristicmentioning

confidence: 99%

Self-Rectifying Twin-Bit RRAM in 3-D Interweaved Cross-Point Array

Chen

Chin

Hsieh

et al. 2015

IEEE J. Electron Devices Soc.

Self Cite

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A new self-rectifying twin-bit RRAM in a novel 3-D interweaved cross-point array has been proposed and demonstrated in 28-nm high-k metal gate CMOS back end of line (BEOL) process. This high density of array architecture with the cell size only 70 × 100 × 187 nm can be manufactured without additional mask or process. The RRAM film is formed by via plug over shifting between two metal lines in back-end process with TaN/TaO x N RRAMs on both sides of a single via. The BEOL RRAM shows large read window between states. Fast switching time of 1 us for set operation and 10 us for reset was demonstrated. Excellent selectivity by its asymmetric IV characteristic enables the twin-bit 1R cells to be efficiently stacked in 3-D cross-point arrays without select transistors.INDEX TERMS Lateral via resistive RAM (LVRRAM), nonvolatile memory (NVM), back end of line process (BEOL), embedded memory self-rectifying RRAM.

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“…Fortunately, benefiting from its excellent * Author to whom any correspondence should be addressed. performance and compatibility with CMOS logic technology, RRAM exhibits great potential to act as the NV storage element in NV latches [6][7][8][9].…”

Section: Introductionmentioning

confidence: 99%

A radiation-hardened hybrid RRAM-based non-volatile latch

Ma¹,

Yang²,

Bi³

et al. 2021

Semicond. Sci. Technol.

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In this paper, a radiation-hardened resistive random-access memory (RRAM)-based non-volatile (NV) latch with a dual-interlocked storage cell is proposed and analyzed. The single-event effects of the proposed NV latch are simulated and discussed. Simulations of the proposed element are based on a 0.18 µm complementary metal-oxide-semiconductor design kit for the peripheral circuit and the voltage threshold adaptive memristor model for the RRAM. The simulation results indicate that the injected charge to induce a single-event upset (SEU) of the proposed NV latch is above 4.5 pC. As compared to the traditional RRAM based NV latch, the proposed NV latch is relatively immune to an SEU. This immunity from the SEU originates from the redundant storage nodes and interlocked feedback mechanism. Moreover, the area overhead of the proposed NV latch (eight transistors in the core storage element) are much lower than other radiation-hardened technology, e.g. TMR or FERST.

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Point twin-bit RRAM in 3D interweaved cross-point array by Cu BEOL process

Cited by 8 publications

References 6 publications

Programmable Mixed-Signal Circuits

Programmable Mixed-Signal Circuits

Self-Rectifying Twin-Bit RRAM in 3-D Interweaved Cross-Point Array

A radiation-hardened hybrid RRAM-based non-volatile latch

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