Polycrystalline silicon metal-oxide-semiconductor field-effect transistor-based stacked multi-layer one-transistor dynamic random-access memory with double-gate structure for the embedded systems

Jang, Won Douk; Yoon, Young Jun; Cho, Min Su; Jung, Jun Hyeok; Lee, Sang Ho; Jang, Jaewon; Bae, Jin‐Hyuk; Kang, In Man

doi:10.7567/1347-4065/ab65d2

Cited by 6 publications

(3 citation statements)

References 27 publications

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“…Also, the grain size assumed 20 nm when GBs exist at the source and drain in the n+ doping region. The trap density of the GBs in the proposed 1T-DRAM used data, as shown in Figure 2 of reference [ 21 ]. There are four traps in the GB: donor-like shallow trap (DST), donor-like deep trap (DDT), acceptor-like shallow trap (AST), and acceptor-like deep trap (ADT).…”

Section: Device Structure and Simulation Methodologymentioning

confidence: 99%

Simulation of Capacitorless DRAM Based on the Polycrystalline Silicon Nanotube Structure with Multiple Grain Boundaries

et al. 2023

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In this study, a capacitorless one-transistor dynamic random-access memory (1T-DRAM), based on polycrystalline silicon (poly-Si) nanotube structure with a grain boundary (GB), is designed and analyzed using technology computer-aided design (TCAD) simulation. In the proposed 1T-DRAM, the 1T-DRAM cell exhibited a sensing margin of 422 μA/μm and a retention time of 213 ms at T = 358 K with a single GB. To investigate the effect of random GBs, it was assumed that the number of GB is seven, and the memory characteristics depending on the location and number of GBs were analyzed. The memory performance rapidly degraded due to Shockley–Read–Hall recombination depending on the location and number of GBs. In the worst case, when the number of GB is 7, the mean of the sensing margin was 194 µA/µm, and the mean of the retention time was 50.4 ms. Compared to a single GB, the mean of the sensing margin and the retention time decreased by 59.7% and 77.4%, respectively.

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Section: Device Structure and Simulation Methodologymentioning

confidence: 99%

Simulation of Capacitorless DRAM Based on the Polycrystalline Silicon Nanotube Structure with Multiple Grain Boundaries

et al. 2023

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“…The geometric parameters of the proposed device are summarized in Table I. In addition, the trap density in GB of the proposed device was used the calibrated data in [17], there are four trap states: donor like shallow trap, donor like deep trap, acceptor like shallow trap, acceptor like deep trap. In this simulation, physics models such as the Shockley-Read-Hall (SRH) recombination, the Hurkx trap-assisted tunneling (TAT), the nonlocal band-to-band tunneling (BTBT) model, the Fermi-Dirac statistical model, the doping-dependent model, and the quantum-confinement effect model are simultaneously applied.…”

Section: Device Structure and Simulation Methodsmentioning

confidence: 99%

Design of Capacitorless DRAM Based on Polycrystalline Silicon Nanotube Structure

et al. 2021

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In this study, a capacitorless one-transistor dynamic random-access memory (1T-DRAM) based on a polycrystalline silicon nanotube structure with a grain boundary (GB) is designed and analyzed using technology computer-aided design (TCAD) simulation. The proposed 1T-DRAM has the improved electrical performances because the outer gate (OG) and the inner gate (IG) effectively control the charges in the channel and body regions. IG has an asymmetric structure with an underlap (Lunderlap) region to reduce the Shockley-Read-Hall (SRH) recombination rate. In the proposed 1T-DRAM, the write "1" operation is performed by band-to-band tunneling between the OG and the IG. The proposed 1T-DRAM cell exhibited a sensing margin of 422 µA/µm and a retention time of 120 ms at T = 358 K.

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“…In recent years, 1T-DRAM devices with poly-Si bodies have been studied to overcome the limitations of silicon 1T-DRAM [ 15 , 16 , 17 , 18 , 19 , 20 , 21 , 22 , 23 , 24 , 25 , 26 ]. Since the poly-Si devices use grain boundaries (GBs) instead of a FB as a charge storage region, they can perform memory operations in a FD-SOI structure [ 15 ].…”

Section: Introductionmentioning

confidence: 99%

Analysis of a Lateral Grain Boundary for Reducing Performance Variations in Poly-Si 1T-DRAM

2020

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A capacitorless one-transistor dynamic random-access memory device that uses a poly-silicon body (poly-Si 1T-DRAM) has been suggested to overcome the scaling limit of conventional one-transistor one-capacitor dynamic random-access memory (1T-1C DRAM). A poly-Si 1T-DRAM cell operates as a memory by utilizing the charge trapped at the grain boundaries (GBs) of its poly-Si body; vertical GBs are formed randomly during fabrication. This paper describes technology computer aided design (TCAD) device simulations performed to investigate the sensing margin and retention time of poly-Si 1T-DRAM as a function of its lateral GB location. The results show that the memory’s operating mechanism changes with the GB’s lateral location because of a corresponding change in the number of trapped electrons or holes. We determined the optimum lateral GB location for the best memory performance by considering both the sensing margin and retention time. We also performed simulations to analyze the effect of a lateral GB on the operation of a poly-Si 1T-DRAM that has a vertical GB. The memory performance of devices without a lateral GB significantly deteriorates when a vertical GB is located near the source or drain junction, while devices with a lateral GB have little change in memory characteristics with different vertical GB locations. This means that poly-Si 1T-DRAM devices with a lateral GB can operate reliably without any memory performance degradation from randomly determined vertical GB locations.

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Polycrystalline silicon metal-oxide-semiconductor field-effect transistor-based stacked multi-layer one-transistor dynamic random-access memory with double-gate structure for the embedded systems

Cited by 6 publications

References 27 publications

Simulation of Capacitorless DRAM Based on the Polycrystalline Silicon Nanotube Structure with Multiple Grain Boundaries

Simulation of Capacitorless DRAM Based on the Polycrystalline Silicon Nanotube Structure with Multiple Grain Boundaries

Design of Capacitorless DRAM Based on Polycrystalline Silicon Nanotube Structure

Analysis of a Lateral Grain Boundary for Reducing Performance Variations in Poly-Si 1T-DRAM

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