Polynomial direct sum masking to protect against both SCA and FIA

Carlet, Claude; Daif, Abderrahman; Guilley, Sylvain; Tavernier, Cédric

doi:10.1007/s13389-018-0194-9

Cited by 7 publications

(2 citation statements)

References 8 publications

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“…Various masking techniques have been developed to either augment or replace Boolean masking, as reported in Table 2. [42] with a goal of protecting against physical glitches. In PM, the basic masking computation is done by function Σ(𝑍𝑋 ), where 𝑍 is a mask vector, 𝑋 is a secret vector, and Σ is XOR operation.…”

Section: Beyond Boolean Maskingmentioning

confidence: 99%

“…This masking scheme provides more algebraic complexity, where the masking computation is done by 𝑋𝐺 ⊕ 𝑍𝐻 , where 𝑋 and 𝑍 are secret input, and random masks respectively, but 𝐺 and 𝐻 represent generator matrices of the vector spaces designated for secret input and masks, respectively. The work in [42] proposed a practical DSM scheme for AES. It detects and corrects errors in a manner that decreases the memory requirements and computation time.…”

Section: Inner Product Masking (Ipm)mentioning

confidence: 99%

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Circuit Masking: From Theory to Standardization, A Comprehensive Survey for Hardware Security Researchers and Practitioners

Covic,

Ganji,

Forte

2021

Preprint

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Side-channel attacks extracting sensitive data from implementations have been considered a major threat to the security of cryptographic schemes. This has elevated the need for improved designs by embodying countermeasures, with masking being the most prominent example. To formally verify the security of a masking scheme, numerous attack models have been developed to capture the physical properties of the information leakage as well as the capabilities of the adversary. With regard to these models, extensive research has been performed to realize masking schemes. These research efforts have led to significant progress in the development of security assessment methodologies and further initiated standardization activities. However, since the majority of this work is theoretical, it is challenging for the more practice-oriented hardware security community to fully grasp and contribute to. To bridge the gap, these advancements are reviewed and discussed in this survey, mainly from the perspective of hardware security. In doing so, a clear taxonomy is provided that is helpful for a systematic treatment of the masking-related topics. By giving an extensive overview of the existing methods, this survey (1) provides a research landscape of circuit masking for newcomers to the field, (2) offers guidelines on which attack model and verification tool to choose when designing masking schemes, and (3) identifies interesting new research directions where masking models and assessment tools can be applied. Thus, this survey serves as an essential reference for hardware security practitioners interested in the theory behind masking techniques, the tools useful to verify the security of masked circuits, and their potential applications.

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Section: Beyond Boolean Maskingmentioning

confidence: 99%

Section: Inner Product Masking (Ipm)mentioning

confidence: 99%