Polysilicon TFT technology for active matrix OLED displays

Stewart, Mark J.; Howell, Robert S.; Pires, L.; Hatalis, Miltiadis K.

doi:10.1109/16.918227

Cited by 304 publications

(156 citation statements)

References 8 publications

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“…With these unparalleled properties, poly-Si has become one of the most important electronic materials used in a vast variety of applications including CMOS transistor, sensing, nanofluidics, thin film transistor (TFT) in displays, photovoltaics, etc. [1][2][3][4][5] Being able to grow high-quality III-V structures on poly-Si could open up a new pathway for low-cost monolithic integrations of optoelectronics with these many applications. In particular, single-crystalline structures that are micron-sized are critical to reduce surface-to-volume ratios.…”

Section: Manuscript Textmentioning

confidence: 99%

Single Crystalline InGaAs Nanopillar Grown on Polysilicon with Dimensions beyond the Substrate Grain Size Limit

Tran

et al. 2013

Nano Lett.

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Monolithic integration of III-V optoelectronic devices with materials for various functionalities inexpensively is always desirable. Polysilicon (poly-Si) is an ideal platform because it is dopable and semi-conducting and can be deposited and patterned easily on a wide range of low cost substrates. However, the lack of crystalline coherency in poly-Si poses an immense challenge for high-quality epitaxial growth. In this work, we demonstrate, for the first time, direct growth of micron-sized InGaAs/GaAs nanopillars on polysilicon. Transmission electron microscopy shows that the micron-sized pillars are single-crystalline and single Wurzite-phase, far exceeding the substrate crystal grain size ~100nm. The high quality growth is enabled by the unique tapering geometry at the base of the nanostructure, which reduces the effective InGaAs/Si contact area to < 40 nm in diameter. The small footprint not only reduces stress due to lattice mismatch but also prevents the nanopillar from nucleating on multiple Si crystal grains. This relaxes the grain size requirement for poly-Si, potentially reducing the cost for poly-Si deposition. Lasing is achieved in the as-grown pillars under optical pumping, attesting their excellent crystalline and optical quality. These promising results open up a pathway for low-cost synergy of optoelectronics with other technologies such as CMOS integrated circuits, sensing, nanofluidics, thin film transistor display, photovoltaics, etc.

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Section: Manuscript Textmentioning

confidence: 99%

Single Crystalline InGaAs Nanopillar Grown on Polysilicon with Dimensions beyond the Substrate Grain Size Limit

Tran

et al. 2013

Nano Lett.

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“…Moreover, the carrier mobility has to be large enough to provide stable operation of large-area displays at required video rate. 5 Usually, the ZnO active layers for TFTs have been deposited by physical vapor deposition ͑PVD͒ such as direct current ͑dc͒ or radio frequency sputtering and pulsed laser deposition. 3,6 Although TFTs with reasonable electrical properties have been reported, the lowest reported value of I off for room temperature PVD ZnO TFT devices has been usually higher than 10 −10 A.…”

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confidence: 99%

High performance thin film transistor with low temperature atomic layer deposition nitrogen-doped ZnO

Lim

Kwon

Kim³

et al. 2007

Applied Physics Letters

175

137

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“…In order to provide stable operation of large-area OLED displays at video rate, the carrier mobility has to be in the range of 5 cm 2 / V s or higher. 1 Furthermore, the threshold voltage of the TFTs has to be stable during device operation. As the threshold voltage of a-Si: H TFTs is not stable due to the creation of electronic defects during operation, 2 a-Si: H TFTs are not suitable for such applications.…”

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confidence: 99%

Influence of contact effect on the performance of microcrystalline silicon thin-film transistors

Chan

Bunte

Stiebig

et al. 2006

Applied Physics Letters

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Microcrystalline silicon thin-film transistors were prepared by plasma-enhanced chemical vapor deposition at substrate temperatures below 200°C. The transistors exhibit electron mobilities of 38cm2∕Vs, threshold voltages in the range of 2V, and subthreshold slopes of 0.3V∕decade. Despite the realization of transistors with high carrier mobility, contact effects limit the performance of the transistors. The influence of the drain and source contacts on device parameters including the mobility, the threshold voltage, and the subthreshold slope will be discussed in detail.

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Polysilicon TFT technology for active matrix OLED displays

Cited by 304 publications

References 8 publications

Single Crystalline InGaAs Nanopillar Grown on Polysilicon with Dimensions beyond the Substrate Grain Size Limit

Single Crystalline InGaAs Nanopillar Grown on Polysilicon with Dimensions beyond the Substrate Grain Size Limit

High performance thin film transistor with low temperature atomic layer deposition nitrogen-doped ZnO

Influence of contact effect on the performance of microcrystalline silicon thin-film transistors

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