Portable, scalable, per-core power estimation for intelligent resource management

Abstract

Abstract-Performance, power, and temperature are now all first-order design constraints. Balancing power efficiency, thermal constraints, and performance requires some means to convey data about real-time power consumption and tem perature to intelligent resource managers. Resource managers can use this information to meet performance goals, maintain power budgets, and obey thermal constraints. Unfortunately, obtaining the required machine introspection is challenging.Most current chips provide no support for per-core power monitoring, and when support exists, it is not exposed to software. We present a methodology for deriving per-core power models using sampled performance counter values and temperature sensor readings. We develop application independent models for four different (four-to eight-core) platforms, validate their accuracy, and show how they can be used to guide scheduling decisions in power-aware resource managers. Model overhead is negligible, and estimations exhibit 1.1 %-5.2% per-suite median error on the NAS, SPEC OMP, and SPEC 2006 benchmarks (and 1.2%-4.4% overall). I. IN TRODUCTIONPower and temperature have joined performance as first order system design constraints. All three influence each other, and together they affect architectural and packaging choices. Power consumption characteristics further influence operating cost, reliability, battery lifetime, and device life time. Balancing power efficiency and thermal constraints with performance requires intelligent resource management, and achieving that balance requires real-time power con sumption and temperature information broken down accord ing to resource, together with software and hardware that can leverage such information to enforce management policies.One logical place to institute intelligent resource manage ment with respect to power, performance, and temperature for chip mUltiprocessor (CMP) systems is at the level of in dividual cores. Measuring run-time power of a single core is problematic, though. Current chips do not support it. Power meters only report total consumption for everything behind a single power cable, and even if such aggregate data were sufficient, the use of meters becomes completely infeasible as machines scale up: coordinating output and feedback from thousands of meters would require a separate (super) computing system. Cycle-level system simulators provide in depth information, but are extremely time consuming and 978-1-4244-7614-511 0/$26.00 ©20 10 IEEE prone to error. Power models implemented on top of the architectural abstractions in such simulators are inherently inaccurate [19], and are impossible to verify when attempt ing to assess new architectural designs. Hardware could be enhanced to measure the current and power draw of a CPU socket, but per-core measurement is difficult when cores share a power plane. Embedding measurement devices on chip is usually infeasible. Even when measurement facilities exist -e.g., the Intel Core i7 [16] features per-core power monitoring at the chip-level -they ar...

Systematic Energy Characterization of CMP/SMT Processor Systems via Automated Micro-Benchmarks

“…This power consumption breakdown is only possible because of the bottom-up modeling methodology. Top-down modeling methods [5,11,23,41] model the processor as a black box. They are able to perform per-core power estimations by gathering per core performance counters.…”

“…The instructions will be load vector instructions (lines [11][12][13][14][15][16][17] that hit equally to the three levels of the cache hierarchy (lines [18][19][20][21][22]. The registers and immediate operands of the instructions will be initialized to a constant value (lines [23][24][25][26] and the dependency distance between the instructions will be assigned randomly (lines [27][28][29]. Finally, the benchmarks synthesizer is invoked 10 times to generate 10 different micro-benchmarks (lines 31-33).…”

The ghost in the machine : don’t let it haunt your software performance measurements

“…Alternative approaches for estimating power consumption based on a power model and activity counters that can be used in place of instrumented power measurements have been proposed [Flinn and Satyanarayanan, 1999;Goel et al, 2010;Lewis et al, 2008;Singh et al, 2009;Stockman et al, 2010]. Software instruments that may be used to estimate power consumption at varying levels of detail are mentioned in Section 4.…”

Additivity: A Selection Criterion for Performance Events for Reliable Energy Predictive Modeling

“…Goel et al [8] divide PMCs into event categories that they believe capture different kinds of microarchitectural activity. The PMCs in each category are then ordered based on their A. Shahid, M. Fahad, R. Reddy, A. Lastovetsky correlation to power consumption using the Spearman's rank correlation.…”

“…[1,9,10] select PMCs manually, based on in-depth study of architecture and empirical analysis. [8,15,18,21,22,27,30] select PMCs that are highly correlated with energy consumption using Spearman's rank correlation coefficient (or Pearson's correlation coefficient) and principal component analysis (PCA). [1,2,15] use variants of linear regression to remove PMCs that do not improve the average model prediction error.…”