Positive Bias Temperature Instability and Hot Carrier Injection of Back Gate Ultra-thin-body In _0.53 Ga _0.47 As-on-Insulator n-Channel Metal-Oxide-Semiconductor Field-Effect Transistor

Abstract

Ultra-thin-body (UTB) In0.53Ga0.47As-on-insulator (In0.53Ga0.47As-OI) structures with thicknesses of 8 and 15 nm are realized by transferring epitaxially grown In0.53Ga0.47As layers to silicon substrates with 15-nmthick Al2O3 as a buried oxide by using the direct wafer bonding method. Back gate n-channel metal-oxidesemiconductor field-effect transistors (nMOSFETs) are fabricated by using these In0.53Ga0.47As-OI structures with excellent electrical characteristics. Positive bias temperature instability (PBTI) and hot carrier injection (HCI) characterizations are performed for the In0.53Ga0.47As-OI nMOSFETs. It is confirmed that the In0.53Ga0.47As-OI nMOSFETs with a thinner body thickness suffer from more severe degradations under both PBTI and HCI stresses. Moreover, the different evolutions of the threshold voltage and the saturation current of the UTB In0.53Ga0.47As-OI nMOSFETs may be due to the slow border traps.

The influence of total ionizing dose on the hot carrier injection of 22 nm bulk nFinFET

“…Because the same charges repel each other, inversion charge density decreases in the adjacent fins. When the number of fins increases, the coupling effect between fins is more signific- ant [7] , the charge density of the inversion layer in the fins decreases, and the channel hot carrier density decreases. And under the effect of the electric field, the impact ionization induced by the hot carrier near the drain is weakened, and the oxide trapped charge and interface state are reduced.…”

“…For another reason, under the action of hot carrier stress, the hot electrons generated by the impact ionization at the drain end will be injected into the gate oxide layer and form oxide trap charges, which is why the V T drifts positively as the stress time increases [7] . Total dose irradiation causes trap holes in the shallow trench isolation (STI) region of the Fin-FET, and the bottom region of the fin generates an additional electric field introduced by irradiation [13] .…”

“…After studying the HCI of 90 nm SOI FinFET with different channel lengths, Jiang pointed out that the degradation mechanism of long-channel devi-ces and short-channel devices is different [6] . Yeh pointed out that 20 nm bulk FinFET with fewer fins show better device characteristics, but the degradation of device parameters caused by hot carriers is more serious [7] . Moreover, different evolutions of the threshold voltage and the saturation current of the UTBB nMOSFETs may be due to the slow border traps [8] .…”

Heterogeneous CMOS Integration of InGaAs-OI nMOSFETs and Ge pMOSFETs Based on Dual-Gate Oxide Technique

“…To prepare the InGaAs-Insulator-Ge substrate, (100) n-Ge wafer (resistivity: 10~20 ohm.cm) and p-In 0.53 Ga 0.47 As/InP wafer (doping: ~10 16 cm −3 ) was manually bonded together in the air, with the 50 nm-thick Al 2 O 3 film deposited by atomic layer deposition (ALD) on both wafers [18]. After annealing process in N 2 ambient at 300 • C for 30 min, InP was selectively etched by HCl solution to fabricate the InGaAs 100 nm-thick Al 2 O 3 -Ge substrate.…”