Positive Bias Temperature Instability Effects in advanced High-k / Metal Gate NMOSFETs

Ioannou, D.P.; Mittl, S.; LaRosa, G.

doi:10.1109/irws.2008.4796085

Cited by 5 publications

(7 citation statements)

References 4 publications

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“…The V t instability and the SILC formation in nFETs with SiO 2 /HfO 2 /metal gate stacks under positive-bias temperature (PBT) stress have been previously studied in some detail [1][2][3][4][5][6][7][8][9][10]. Both degradation phenomena have been related to electron trapping in bulk oxide defects and oxygen vacancies in the HfO 2 layer were proposed as one of the primary defects [1,2].…”

Section: Introductionmentioning

confidence: 99%

Stress-induced leakage current and defect generation in nFETs with HfO<inf>2</inf>/TiN gate stacks during positive-bias temperature stress

Cartier

Kerber

2009

2009 IEEE International Reliability Physics Symposium

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The stress-induced leakage current (SILC) in nFETs with SiO 2 /HfO 2 /TiN dual-dielectric gate stacks with metal electrodes is studied during positive-bias temperature stress at high temperatures and at high gate stress voltage. It is shown that strong defect creation in the HfO 2 causes a linear increase of the SILC with stress time. The SILC generation is found to be thermally activated with an activation energy, E a ~ 1 eV. In addition, the SILC formation exhibits a strong correlation with the threshold voltage (V t ) instability ΔI g /I g ~ dV t 3 . Both degradation phenomena show a strong hysteretic behavior with gate bias; the SILC and V t -degradation are observed to be substantially reduced by applying a negative gate bias after stress. All these observations may be rationalized in terms of charge trapping in shallow HfO 2 defects -such as oxygen vacancy -and by the generation of new shallow defects during stress. The defect generation process has a low activation energy, likely because of thin-film effects. Therefore, the SILC and the V t instability are large under accelerated TDDB test conditions. It is also shown that the observed low activation energy in combination with the reversibility of the SILC has important implications for dielectric breakdown detection in dual-dielectric gate stacks.

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Section: Introductionmentioning

confidence: 99%

Stress-induced leakage current and defect generation in nFETs with HfO<inf>2</inf>/TiN gate stacks during positive-bias temperature stress

Cartier

Kerber

2009

2009 IEEE International Reliability Physics Symposium

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“…1b. When measured with 1 ms delay, the time exponent declines as voltage increases [1], making it impossible for predicting the long term PBTI under real use conditions [14]. The apparent time exponent is close to a constant, when measurement delay is minimized to 3 µs .…”

Section: Introductionmentioning

confidence: 99%

“…geing has become a critical concern for CMOS technologies as scaling is reaching nano-scale regime [1][2][3][4][5][6][7][8]. Thorough examination and certification of reliable operation throughout the entire application lifetime is required during design.…”

Section: Introductionmentioning

confidence: 99%

“…Extensive efforts have been made in investigating the Negative Bias Temperature Instability (NBTI) for pFETs. The recent use of the multi-layer gate material, however, has led to considerable Positive Bias Temperature Instability (PBTI) for nFETs [1][2][3][4][5][6][7][8]. From the application perspective, it has been reported that PBTI can be the dominating reliability issue for Field-Programmable Gate Arrays (FPGAs) [10] and Ring Oscillators (RO) [11].…”

Section: Introductionmentioning

confidence: 99%

“…Despite industry-wide characterization of various aspects of PBTI phenomena and general consensus regarding its empirical features [1][2][3][4][5][6][7][8][9][10][11], the detailed mechanism of the degradation is not fully understood. Charging of pre-existing traps and/or generating new traps in the dielectric are considered to be the root of PBTI [12].…”

Section: Introductionmentioning

confidence: 99%

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