Post-silicon code coverage for multiprocessor system-on-chip designs

Balston, Kyle; Karimibiuki, Mehdi; Hu, Alan J.; Ivanov, A.; Wilton, Steven J. E.

doi:10.1109/tc.2012.163

Cited by 13 publications

(7 citation statements)

References 11 publications

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“…The validation methodologies followed in today's design are working towards answering such questions. Coverage analysis provides key metrics to quantify validation effectiveness [3] [8] [11].…”

Section: Coveragementioning

confidence: 99%

“…Code coverage: Code coverage quantifies the lines of RTL code exercised [3] [12]. The main code coverage types include statement coverage, branch coverage, and path coverage.…”

Section: Coverage Metricsmentioning

confidence: 99%

“…The design must include additional coverage monitoring hardware to enable coverage analysis in post-silicon. On-chip coverage logic increases observability, but does not contribute to the functional logic; hence, it is controlled and limited [3]. Qualitative post-silicon validation can significantly reduce costs and enable shorter time-to-market.…”

Section: Introductionmentioning

confidence: 99%

“…First, to improve the quality of validation by enhancing bug-hunting methods, such as the hybrid quick error detection technique [4] and by improving the on-chip debug capabilities [5]- [7]. Second, to reduce the on-chip logic required for coverage monitors [3] [8]- [10]. However, much work must be carried out in defining the coverage metrics specific for post-silicon.…”

Section: Introductionmentioning

confidence: 99%

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Unified Coverage Methodology for SoC Post-Silicon Validation

Aslan¹,

Chandrai²,

Siddaiah³

2016

OPJ

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The System-on-Chip's increased complexity and shortened design cycle calls for innovation in design and validation. A high quality System-on-Chip creates distinction and position in the market, and validation is the key to a quality product. Validation consumes >60% of the product cycle. Therefore, validation should be carried out efficiently. Validation must be quantified to aid in determining its quality. Pre-silicon uses various coverage metrics for quantifying the validation. The available on-chip coverage logic limits the use of pre-silicon-like coverage metrics in post-silicon. Although on-chip coverage logic increases observability, it does not contribute to the functional logic; hence, they are controlled and limited. Discounting the need for the on-chip coverage logic, the question to be answered is whether or not these pre-silicon coverage metrics applicable to post-silicon. We discuss the reasons for limited applicability of pre-silicon coverage metrics in post-silicon. This paper presents a unified SoC post-silicon coverage methodology centered on functional coverage metrics.

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Section: Coveragementioning

confidence: 99%

“…Code coverage: Code coverage quantifies the lines of RTL code exercised [3] [12]. The main code coverage types include statement coverage, branch coverage, and path coverage.…”

Section: Coverage Metricsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Unified Coverage Methodology for SoC Post-Silicon Validation

Aslan¹,

Chandrai²,

Siddaiah³

2016

OPJ

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“…One common approach to post-silicon coverage evaluation is to use in-silicon coverage monitors [11]- [13]. However, adding coverage monitors to the silicon is costly in terms of timing, power, and area [14].…”

Section: Related Workmentioning

confidence: 99%

Coverage evaluation of post-silicon validation tests with virtual prototypes

Cong

Yang

et al. 2014

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2014

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Abstract-High-quality tests for post-silicon validation should be ready before a silicon device becomes available in order to save time spent on preparing, debugging and fixing tests after the device is available. Test coverage is an important metric for evaluating the quality and readiness of post-silicon tests. We propose an online-capture offline-replay approach to coverage evaluation of post-silicon validation tests with virtual prototypes for estimating silicon device test coverage. We first capture necessary data from a concrete execution of the virtual prototype within a virtual platform under a given test, and then compute the test coverage by efficiently replaying this execution offline on the virtual prototype itself. Our approach provides early feedback on quality of post-silicon validation tests before silicon is ready. To ensure fidelity of early coverage evaluation, our approach have been further extended to support coverage evaluation and conformance checking in the post-silicon stage. We have applied our approach to evaluate a suite of common tests on virtual prototypes of five network adapters. Our approach was able to reliably estimate that this suite achieves high functional coverage on all five silicon devices.

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Utilization of Debug Infrastructure for Post-Silicon Coverage Analysis

Farahmandi

Mishra

2018

Post-Silicon Validation and Debug

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Post-silicon code coverage for multiprocessor system-on-chip designs

Cited by 13 publications

References 11 publications

Unified Coverage Methodology for SoC Post-Silicon Validation

Unified Coverage Methodology for SoC Post-Silicon Validation

Coverage evaluation of post-silicon validation tests with virtual prototypes

Utilization of Debug Infrastructure for Post-Silicon Coverage Analysis

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