Post-silicon conformance checking with virtual prototypes

Li, Lei; Xie, Fei; Cong, Kai

doi:10.1145/2463209.2488770

Cited by 16 publications

(9 citation statements)

References 15 publications

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“…For high-level synthesis, symbolic execution is used for executing both high-level C design and low-level RTL design symbolically and then equivalence checking is conducted. For post-silicon functional validation, symbolic execution of virtual devices has been employed to support test generation [11,27,28] and conformance checking [12,29,30].…”

Section: B Symbolic Execution On Hardware Domainmentioning

confidence: 99%

Automatic generation of high-coverage tests for RTL designs using software techniques and tools

Feng

Huang

2016

2016 IEEE 11th Conference on Industrial Electronics and Applications (ICIEA)

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Abstract-Register Transfer Level (RTL) design validation is a crucial stage in the hardware design process. We present a new approach to enhancing RTL design validation using available software techniques and tools. Our approach converts the source code of a RTL design into a C++ software program. Then a powerful symbolic execution engine is employed to execute the converted C++ program symbolically to generate test cases. To better generate efficient test cases, we limit the number of cycles to guide symbolic execution. Moreover, we add bit-level symbolic variable support into the symbolic execution engine. Generated test cases are further evaluated by simulating the RTL design to get accurate coverage. We have evaluated the approach on a floating point unit (FPU) design. The preliminary results show that our approach can deliver highquality tests to achieve high coverage.

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Section: B Symbolic Execution On Hardware Domainmentioning

confidence: 99%

Automatic generation of high-coverage tests for RTL designs using software techniques and tools

Feng

Huang

2016

2016 IEEE 11th Conference on Industrial Electronics and Applications (ICIEA)

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“…The Phase 1 testing tests individual components of DUT (lines [15][16][17][18][19][20][21][22][23][24][25][26][27][28][29][30][31][32]. The components that are not tested are left in their original state.…”

Section: Unit-level Testingmentioning

confidence: 99%

VDTest

Cohen

2016

Proceedings of the 38th International Conference on Software Engineering

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The use of virtual devices in place of physical hardware is increasing in activities such as design, testing and debugging. Yet virtual devices are simply software applications, and like all software they are prone to faults. A full system simulator (FSS), is a class of virtual machine that includes a large set of virtual devices -enough to run the full target software stack. Defects in an FSS virtual device may have cascading effects as the incorrect behavior can be propagated forward to many different platforms as well as to guest programs. In this work we present VDTest, a novel framework for testing virtual devices within an FSS. VDTest begins by generating a test specification obtained through static analysis. It then employs a two-phase testing approach to test virtual components both individually and in combination. It leverages a differential oracle strategy, taking advantage of the existence of a physical or golden device to eliminate the need for manually generating test oracles. In an empirical study using both open source and commercial FSSs, we found 64 faults, 83% more than random testing.

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“…In previous work [7], we have developed an approach to post-silicon conformance checking of a silicon device with its virtual device. The conformance between the silicon and virtual devices is defined over their interface states.…”

Section: Post-silicon Conformance Checkingmentioning

confidence: 99%

Coverage evaluation of post-silicon validation tests with virtual prototypes

Cong

Yang

et al. 2014

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2014

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Abstract-High-quality tests for post-silicon validation should be ready before a silicon device becomes available in order to save time spent on preparing, debugging and fixing tests after the device is available. Test coverage is an important metric for evaluating the quality and readiness of post-silicon tests. We propose an online-capture offline-replay approach to coverage evaluation of post-silicon validation tests with virtual prototypes for estimating silicon device test coverage. We first capture necessary data from a concrete execution of the virtual prototype within a virtual platform under a given test, and then compute the test coverage by efficiently replaying this execution offline on the virtual prototype itself. Our approach provides early feedback on quality of post-silicon validation tests before silicon is ready. To ensure fidelity of early coverage evaluation, our approach have been further extended to support coverage evaluation and conformance checking in the post-silicon stage. We have applied our approach to evaluate a suite of common tests on virtual prototypes of five network adapters. Our approach was able to reliably estimate that this suite achieves high functional coverage on all five silicon devices.

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Post-silicon conformance checking with virtual prototypes

Cited by 16 publications

References 15 publications

Automatic generation of high-coverage tests for RTL designs using software techniques and tools

Automatic generation of high-coverage tests for RTL designs using software techniques and tools

VDTest

Coverage evaluation of post-silicon validation tests with virtual prototypes

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