Post-Silicon Validation in the SoC Era: A Tutorial Introduction

Mishra, Prabhat; Morad, Ronny; Ziv, Avi; Ray, Sandip

doi:10.1109/mdat.2017.2691348

Cited by 57 publications

(5 citation statements)

References 37 publications

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“…Validation of VLSI is carried out in pre-silicon or postsilicon stages of the development flow [58,66]. The development starts with a specification provided by the customer and then a designer implements a behavioral level design that is specifically used for pre-silicon validation or verification using simulation.…”

Section: Related Work and Backgroundmentioning

confidence: 99%

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Model-based ideal testing of hardware description language (HDL) programs

et al. 2021

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An ideal test is supposed to show not only the presence of bugs but also their absence. Based on the Fundamental Test Theory of Goodenough and Gerhart (IEEE Trans Softw Eng SE-1(2): [156][157][158][159][160][161][162][163][164][165][166][167][168][169][170][171][172][173] 1975), this paper proposes an approach to model-based ideal testing of hardware description language (HDL) programs based on their behavioral model. Test sequences are generated from both original (fault-free) and mutant (faulty) models in the sense of positive and negative testing, forming a holistic test view. These test sequences are then executed on original (fault-free) and mutant (faulty) HDL programs, in the sense of mutation testing. Using the techniques known from automata theory, test selection criteria are developed and formally show that they fulfill the major requirements of Fundamental Test Theory, that is, reliability and validity. The current paper comprises a preparation step (consisting of the sub-steps model construction, model mutation, model conversion, and test generation) and a composition step (consisting of the sub-steps pre-selection and construction of Ideal test suites). All the steps are supported by a toolchain that is already implemented and is available online. To critically validate the proposed approach, three case studies (a sequence detector, a traffic light controller, and a RISC-V processor) are used and the strengths and weaknesses of the approach are discussed. The proposed approach achieves the highest mutation score in positive and negative testing for all case studies in comparison with two existing methods (regular expression-based test generation and context-based random test generation), using four different techniques. KeywordsModel-based testing • Ideal testing • Mutation testing • Behavioral model • Hardware description language Communicated by Dr Benoit Baudry.

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Section: Related Work and Backgroundmentioning

confidence: 99%

“…RTL can be also used for functional test generation. In postsilicon validation, a silicon die, a chip not packaged yet, is validated against the specification for detection of the errors missed during the pre-silicon validation stage [66].…”

Section: Related Work and Backgroundmentioning

confidence: 99%

Model-based ideal testing of hardware description language (HDL) programs

et al. 2021

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“…In modern SoC design, pre-silicon verification is the most resource-intensive phase involving functional correctness and constraint checks on the SoC [19]. Considering a three layered approach to SoC design with hardware, resource management and application layers, both, discrete-event [13], [14] and cycle-accurate [15]- [17] based simulation approaches address the challenges involving each layer in isolation.…”

Section: Literature Surveymentioning

confidence: 99%

User-Space Emulation Framework for Domain-Specific SoC Design

Mack¹,

Kumbhare²,

NK³

et al. 2020

Preprint

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In this work, we propose a portable, Linux-based emulation framework to provide an ecosystem for hardwaresoftware co-design of Domain-specific SoCs (DSSoCs) and enable their rapid evaluation during the pre-silicon design phase. This framework holistically targets three key challenges of DSSoC design: accelerator integration, resource management, and application development. We address these challenges via a flexible and lightweight user-space runtime environment that enables easy integration of new accelerators, scheduling heuristics, and user applications, and we illustrate the utility of each through various case studies. With signal processing (WiFi and RADAR) as the target domain, we use our framework to evaluate the performance of various dynamic workloads on hypothetical DSSoC hardware configurations composed of mixtures of CPU cores and FFT accelerators using a Zynq UltraScale+ TM MPSoC. We show the portability of this framework by conducting a similar study on an Odroid platform composed of big.LITTLE ARM clusters. Finally, we introduce a prototype compilation toolchain that enables automatic mapping of unlabeled C code to DSSoC platforms. Taken together, this environment offers a unique ecosystem to rapidly perform functional verification and obtain performance and utilization estimates that help accelerate convergence towards a final DSSoC design.

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“…Then, after going through the place & route process, the synthesized RTL may be mapped on a reconfigurable fabric to be verified again (on-board verification) [1]. These three verification stages are considered pre-silicon activities [2], whose objective differs from post-silicon activities, which creates a gap between both; the first is driven by models, whilst the second ensures that the silicon works properly under actual conditions. In contrast, early pre-silicon activities omit important details of the physical layer, and designers are forced to use prototyping platforms, such as FPGAs.…”

Section: Introductionmentioning

confidence: 99%

FPGA-Based Solution for On-Board Verification of Hardware Modules Using HLS

et al. 2020

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High-Level Synthesis (HLS) tools provide facilities for the development of specialized hardware accelerators (HWacc). However, the verification stage is still the longest phase in the development life-cycle. Unlike in the software industry, HLS tools lack testing frameworks that could cover the whole design flow, especially the on-board verification stage of the generated RTL. This work introduces a framework for on-board verification of HLS-based modules by using reconfigurable systems and Docker containers with the aim to automate the verification process and preserve a clean testing environment, making the testbed reusable across different stages of the design flow. Moreover, our solution features a mechanism to check timing requirements of the HWacc. We have applied our solution to the C-kernels of the CHStone Benchmark on a Zedboard, in which the on-board verification process has been accelerated up to four times.

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Post-Silicon Validation in the SoC Era: A Tutorial Introduction

Cited by 57 publications

References 37 publications

Model-based ideal testing of hardware description language (HDL) programs

Model-based ideal testing of hardware description language (HDL) programs

User-Space Emulation Framework for Domain-Specific SoC Design

FPGA-Based Solution for On-Board Verification of Hardware Modules Using HLS

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