Post Simulation of High Speed Sense Amplifiers using 45 nm CMOS Technology Used in IOT Application

Singh, Thakurendra; Tomar, V. K.

doi:10.1109/parc52418.2022.9726536

Cited by 2 publications

(1 citation statement)

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“…Journal of Nanomaterials CMOS process technology is widely used in analog and digital hardware design due to certain advantages such as CMOS devices are mechanically robust, nonsalicided poly layer is generally used for fabrication of linear resistors in analog CMOS IC design, CMOS hardware is highly integrable and compact due to sharing of diffusion regions, and very low values of static power dissipation are there with the availability of high noise margin [32][33][34][35][36][37][38][39]. Reason for choosing 180 nm technology is that cut off frequencies of 180 nm nMOSFETs ranges from 50 GHz to 80 GHz for diverse layout states which lies in the of operating frequency range of the proposed mixer [40].…”

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confidence: 99%

Low‐Voltage Low Noise Figure Down‐Conversion Mixer for Band #1 of MB‐OFDM System in 180 nm Complementary Metal Oxide Semiconductor Technology

Chaturvedi

Kumar

Meena

et al. 2022

Journal of Nanomaterials

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Low-voltage design is a challenge for Gilbert cell-based mixers due to stacking transconductance and switching stage. This work addresses this issue by proposing a design of a low-voltage down-conversion mixer for band #1 of multiband orthogonal frequency division multiplexing (MB-OFDM) system in 180 nm complementary metal oxide semiconductor (CMOS) technology. The mixer is tuned at band #1 at RF frequency of 3.432 GHz and IF frequency of 264 MHz. The proposed mixer uses folded cascode connection of LO and RF in order to increase headroom and to reduce the DC supply voltage for low-voltage operation. Common gate configuration is used at RF transconductance stage to enhance the input bandwidth of the mixer. RF and LO ports are matched to 50 Ω using differential T and LC matching, respectively. The resistive source denegation technique is used to linearize transconductance with respect to the bias point. The common source stage is used at the IF port as a buffer cum matching circuit it. The simulation results of the mixer show the maximum conversion gain of 9.76 dB, 1 dB compression point (P1dB) of -16.25 dBm, the third-order input intercept point (IIP3) of -4.70 dBm, an SSB noise figure of 9.036 dB, and S11of -19.490 dB at the supply voltage of 1.2 V. Excluding off chip components, proposed mixer records an active area of 926.35 μm2.

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