Postpass Code Optimization of Pipeline Constraints

Abstract

Pipeline interlocks are used in a pipelined architecture to prevent the execution of a machine instruction before its operands are available. An alternative to this complex piece of hardware is to rearrange the instructions at compile time to avoid pipeline interlocks. This problem is called code reorganization and is studied here. The basic problem of reorganization of machine-level instructions at compile time is shown to be NP-complete. A heuristic algorithm is proposed, and its properties and effectiveness are explored. Empirical data from MIPS, a VLSI processor design, are given. The impact of code reorganization techniques on the rest of a compiler system is discussed.

Instruction Scheduling with Release Times and Deadlines on ILP Processors

“…By using induction and the properties of forward scheduling and backward scheduling, we can prove the fol- v [5,12] v [6,15] v [6,15] v [8,15] 6 v [6, 15] v [8,10] v [8,10] v [4,8] v [5,13] v [2,6] v [3,7] Proof Suppose that there exists a feasible schedule σ ′ , but a schedule σ computed by our algorithm is not feasible. Let v k be the first late instruction and t the earliest integer time point satisfying 1) there are m k (σ(v k ) − t) instructions scheduled in the time interval [t, σ(v k )) on m k functional unit of type R(v k ) in σ, where m k is the number of functional units of type R(v k ), and 2) for each instruction …”

“…In non-real-time applications, the objective of instruction scheduling is to find a shortest schedule for a set of instructions. This problem is NP-complete even if the target processor has only one functional unit and latencies can be arbitrarily large [12,13].…”

“…Suppose that our algorithm has computed the 0-successortree consistent deadline of v 6 which is 7, we show how our algorithm computes the 4-successor-tree-consistent dead- [5,13] v [8,10] v [8,10] v [4,8] v [5,12] v [2,6] v [1,4] Lastly it applies disjoint union-find algorithm to find the successor-tree-consistent deadline which is 11. The l max (v i )-successor-tree-consistent deadline of each instruction v i is shown in Figure 6 where y in [x, y] beside each instruction v i is the l max (v i )-successor-tree-consistent deadline of v i .…”

Instruction-Level Parallel Processing: History, Overview, and Perspective

“…Scheduling for such processors, whether RISC or CISC, has generally been less ambitious and more ad hoc than that for VLIW processors [183][184][185]98,186]. This was a direct consequence of the lack of parallelism in those machines and the corresponding lack of opportunity for the scheduler to make a big difference.…”

“…However, in the context of pipelined or multiple-issue processors, where instruction scheduling is important, the issue of the phase-ordering between it and register allocation has been a topic of much debate. There are advocates both for performing register allocation before scheduling [185,200,192] as well as for performing it after scheduling [183,[201][202][203]. Each phase-ordering has its advantages and neither one is completely satisfactory.…”