Postsilicon Trace Signal Selection Using Machine Learning Techniques

Rahmani, Kamran; Ray, Sandip; Mishra, Prabhat

doi:10.1109/tvlsi.2016.2593902

Cited by 25 publications

(19 citation statements)

References 12 publications

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“…Trace buffer is widely used to improve the observability of circuit and thus assist postsilicon debug and analysis [16,[29][30][31]. It is a buffer that traces (records) some of the internal signals in a silicon chip during runtime.…”

Section: Trace Buffermentioning

confidence: 99%

“…• BufferWidth=8: {dcnt [2], ld r, w3 [2], w3[1], w3 [30], w3 [27], w3 [17], w3[13]} • BufferWidth=16: {dcnt [2], ld r, w3 [4], w3 [29], w3 [27], w3 [23], w3 [22], w3 [18], w3 [16], w3 [15], w3 [14], w3 [13], w3 [12], w3 [10], w1 [9], w3[8]} • BufferWidth=32: {dcnt [2], ld r, sa03 [7], sa13 [7], w3 [7], w3 [6], w3 [3], w3 [2], w3[1], w3 [31], w3 [30], w2 [29], w3 [27], w3 [26], w3 [25], w3 [24], w3 [23], w3 [22], w3 [21], w3 [20], w3 [18], w2 [17], w3 [16], w3 [15], w0 [14], w3 [13], w3 [12], w3 [11], w3 [10], w3 [9], w3 [8], w3[0]} …”

Section: (2) Attack With Rtl Implementationmentioning

confidence: 99%

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Trace Buffer Attack on the AES Cipher

Huang

Mishra

2017

J Hardw Syst Secur

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Since the standardization of AES/Rijndael symmetric-key cipher by NIST in 2001, it gained widespread acceptance in various protocols and withstood intense scrutiny from the theoretical cryptanalysts. From the physical implementation point of view, however, AES remained vulnerable. Practical attacks on AES via fault injection, differential power analysis, scan-chain and cacheaccess timing have been demonstrated so far. In this paper, we propose a novel and effective attack, termed Trace Buffer Attack. Trace buffers are extensively used for postsilicon debug of integrated circuits. We identify the trace buffer as a source of information leakage. We first report the detailed process of trace buffer attack assuming that the register-transfer level (RTL) implementation is available. We further analyze the AES encryption algorithm and Rijndael's key expansion algorithm, and illustrate that trace buffer attack is feasible without implementation (RTL) knowledge. Our experimental results show that trace buffer attack is capable of partially recovering the secret keys of different AES implementations.

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Section: Trace Buffermentioning

confidence: 99%

Section: (2) Attack With Rtl Implementationmentioning

confidence: 99%

Trace Buffer Attack on the AES Cipher

Huang

Mishra

2017

J Hardw Syst Secur

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“…There has been recent research on machine learning applications to some areas of post-silicon validation. In [10], authors propose a trace signal simulation-based selection technique that exploits machine learning to efficiently identify a small set of key traceable signals, reducing the simulation cost. An algorithm that applies anomaly detection techniques is proposed in [9] for post-silicon bug diagnosis.…”

Section: Machine Learning In Post-silicon Validationmentioning

confidence: 99%

Post-Silicon Receiver Equalization Metamodeling by Artificial Neural Networks

Rangel-Patiño

Rayas‐Sánchez

Viveros-Wacher

et al. 2019

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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As microprocessor design scales to the 10 nm technology and beyond, traditional pre-and post-silicon validation techniques are unsuitable to get a full system functional coverage. Physical complexity and extreme technology process variations severely limits the effectiveness and reliability of presilicon validation techniques. This scenario imposes the need of sophisticated post-silicon validation approaches to consider complex electromagnetic phenomena and large manufacturing fluctuations observed in actual physical platforms. One of the major challenges in electrical validation of high-speed input/output (HSIO) links in modern computer platforms lies in the physical layer (PHY) tuning process, where equalization techniques are used to cancel undesired effects induced by the channels. Current industrial practices for PHY tuning in HSIO links are very time consuming since they require massive lab measurements. An alternative is to use machine learning techniques to model the PHY, and then perform equalization using the resultant surrogate model. In this paper, a metamodeling approach based on neural networks is proposed to efficiently simulate the effects of a receiver equalizer PHY tuning settings. We use several design of experiments techniques to find a neural model capable of approximating the real system behavior without requiring a large amount of actual measurements. We evaluate the models performance by comparing with measured responses on a real server HSIO link.

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“…However, use of less simulations to identify the top signals impacts the restoration performance of the final selected set of trace signals. Recently, a learning-based approach [1] has been proposed where it applies machine learning regression techniques to the circuit under test to reduce the overhead of O(N 2 ) simulations by O(N 2 ) fast predictions, where N is the number of flip-flops in the design. However, it still needs O(N ) simulations, typically thousands or millions of simulations of the design, to train the selection model, which limits its applicability on large industry scale circuits.…”

Section: Fast Model Training and Predictionsmentioning

confidence: 99%

“…Rahmani et al [1] proposed an approach that utilizes regression techniques to reduce the number of simulations from O(N 2 ) in Chatterjee et al [6] to O(N ). However, it is still computationally prohibitive in large industry circuits.…”

Section: Background and Motivationmentioning

confidence: 99%

Feature-based Signal Selection for Post-silicon Debug using Machine Learning

Rahmani

Mishra

2017

IEEE Trans. Emerg. Topics Comput.

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A key challenge of post-silicon validation methodology is to select a limited number of trace signals that are effective during post-silicon debug. Structural analysis used by traditional signal selection techniques are fast but lead to poor restoration quality. In contrast, simulation-based selection techniques provide superior restorability but incur significant computation overhead. While early work on machine learning based signal selection is promising [1], it is still not applicable on large industrial designs since it needs thousands of simulations of large and complex designs. In this paper, we propose a signal selection technique that addresses the scalability issue of simulation-based techniques while maintaining a high restoration performance. The basic idea is to train a machine learning framework using a small set of circuits, and apply the trained model to the bigger circuit under test, without any need for simulating the large industry-scale designs. This paper makes two fundamental contributions: i) this is the first attempt to show that learning from small related circuits can be useful for signal selection, and ii) this is the first automated signal selection approach that is applicable on industrial designs without sacrificing restoration quality. Experimental results indicate that our approach can improve restorability by up to 135.4% (8.8% on average) while significantly reduce (up to 37X, 16.6X on average) the runtime compared to existing signal selection approaches.

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Postsilicon Trace Signal Selection Using Machine Learning Techniques

Cited by 25 publications

References 12 publications

Trace Buffer Attack on the AES Cipher

Trace Buffer Attack on the AES Cipher

Post-Silicon Receiver Equalization Metamodeling by Artificial Neural Networks

Feature-based Signal Selection for Post-silicon Debug using Machine Learning

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