Potential of a novel double-sided fully-depleted silicon-on-insulator CMOS architecture for the next-generation monolithic 3D CPUs and SOCs

Tarakji, A.; Chaudhary, Nirmal

doi:10.1109/s3s46989.2019.9320673

2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) 2019

DOI: 10.1109/s3s46989.2019.9320673

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Potential of a novel double-sided fully-depleted silicon-on-insulator CMOS architecture for the next-generation monolithic 3D CPUs and SOCs

A. Tarakji

Nirmal Chaudhary²

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2022

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An Investigation of the Effect of the Work-Function Variation of a Monolithic 3D Inverter Stacked with MOSFETs

Lee

2022

Micromachines

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The effect of the work-function variation (WFV) of metal-oxide-semiconductor field-effect transistor (MOSFET) gates on a monolithic 3D inverter (M3DINV) structure is investigated in the current paper. The M3DINV has a structure in which MOSFETs are sequentially stacked. The WFV effect of the top- and bottom-tier gates on the M3DINV is investigated using technology computer-aided design (TCAD) and a Monte-Carlo sampling simulation of TCAD. When the interlayer dielectric thickness (TILD) changes from 5 to 100 nm, electrical parameters, such as the threshold voltage, subthreshold swing, on-current, and off-current of the top-tier N-MOSFET and the parameter changes by the change in gate voltage of the bottom-tier P-MOSFET, are investigated. As TILD decreases below about 30 nm, the means and standard deviations of the electrical parameters rapidly increase. This means that the coupling and its distribution are relatively large in the regime and thus should be well considered for M3D circuit simulation. In addition, due to the increase in standard deviation, the WFV effect of both the top- and bottom-tier MOSFET gates was observed to be greater than those of only the top-tier MOSFET gates and only the bottom-tier MOSFET gates.

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An Investigation of the Effect of the Work-Function Variation of a Monolithic 3D Inverter Stacked with MOSFETs

Lee

2022

Micromachines

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show abstract

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Potential of a novel double-sided fully-depleted silicon-on-insulator CMOS architecture for the next-generation monolithic 3D CPUs and SOCs

Cited by 1 publication

References 2 publications

An Investigation of the Effect of the Work-Function Variation of a Monolithic 3D Inverter Stacked with MOSFETs

An Investigation of the Effect of the Work-Function Variation of a Monolithic 3D Inverter Stacked with MOSFETs

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