Power Analysis of FPGAs: How Practical Is the Attack?

Abstract

Abstract. Recent developments in information technologies made the secure transmission of digital data a critical design point. Large data flows have to be exchanged securely and involve encryption rates that sometimes may require hardware implementations. Reprogrammable devices such as Field Programmable Gate Arrays are highly attractive solutions for hardware implementations of encryption algorithms and several papers underline their growing performances and flexibility for any digital processing application. Although cryptosystem designers frequently assume that secret parameters will be manipulated in closed reliable computing environments, Kocher et al. stressed in 1998 that actual computers and microchips leak information correlated with the data handled. Side-channel attacks based on time, power and electromagnetic measurements were successfully applied to the smart card technology, but we have no knowledge of any attempt to implement them against FPGAs. This paper examines how monitoring power consumption signals might breach FPGA-security. We propose first experimental results against FPGA-implementations of cryptographic algorithms in order to confirm that power analysis has to be considered as a serious threat for FPGA security. We also highlight certain features of FPGAs that increase their resistance against side-channel attacks.

Overview of securing multimedia content using efficient encryption methods and modes

“…Power analysis attack measures power consumption of device during encryption at regions where traces of using secret key increases (Kocher et al, 1999). FPGA implementations of ECC (Örs et al, 2003), RSA, AES and DES are broken by such attacks (Standaert et al, 2003;Standaert et al, 2004a;Standaert et al, 2004b).…”

Trojan Side-Channels: Lightweight Hardware Trojans through Side-Channel Engineering

“…To demonstrate the applicability of the proposed TSC, we implement an entire AES cryptosystem and a TSC using the linear feedback shift register (LFSR) shown in Figure 2 on running at 50 MHz. We use a 1 Ω serial current-sensing resistor to probe the power consumption of the FPGA core, similar to the experimental setups described in [22,23]. The transient power traces are measured by an Agilent Infiniium 54832D oscilloscope.…”

DPA resistance for light-weight implementations of cryptographic algorithms on FPGAs

“…In subsequent years many successful DPA attacks against cryptographic algorithms implemented in software and on ASICs were published. However, four years later the first results on successful DPA attacks against DES and RSA [3] and ECC [4] implementations on FPGAs were reported. The first design methodology to secure ASIC and FPGA implementations using DDL was published by Tiri in 2004 [5].…”