Power and chip-area aware network-on-chip simulation

Abstract

Among different communication architectures employed in Multi-Processor Systems-on-Chip (MPSoC), Network-on-Chip (NoC) is recognized as a state of the art paradigm that can overcome on-chip communication challenges. In this thesis, we introduce the simulation of NoC systems. The structure of a new SystemC based NoC simulator (FANOOS) is presented in this thesis. We discuss various components of the simulator by presenting their SystemC code. We also provide an analytical methodology that employs the micro-architectural level of NoC routers and links by considering their power and chip are requirements. An evaluation flow for early stage design of NoC is introduced.