Power and Energy Characterization of an Open Source 25-Core Manycore Processor

McKeown, Michael; Lavrov, Alexey; Shahrad, Mohammad; Jackson, Paul J.; Fu, Yaosheng; Balkind, Jonathan; Nguyen, Tri Minh; Lim, Katie; Zhou, Yanqi; Wentzlaff, David

doi:10.1109/hpca.2018.00070

Cited by 27 publications

(19 citation statements)

References 55 publications

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“…This corresponds to two LLC downgrades (one in each direction) needed after the head pointer for each queue has been updated. This downgrade latency is in line with the L2 cache hit latency observed in a previous characterisation of the Piton processor [34], which was an ASIC implementation of the OpenPiton platform we started our work from. A downgrade round trip will take additional cycles over an LLC hit as the LLC must then request the downgrade itself from the BPC.…”

Section: Resultssupporting

confidence: 78%

Byoc

Balkind

Lim

Schaffner

et al. 2020

Proceedings of the Twenty-Fifth International Conference on Architectural Support for Programming Languages and Operating Syste

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Heterogeneous architectures and heterogeneous-ISA designs are growing areas of computer architecture and system software research. Unfortunately, this line of research is significantly hindered by the lack of experimental systems and modifiable hardware frameworks. This work proposes BYOC, a "Bring Your Own Core" framework that is specifically designed to enable heterogeneous-ISA and heterogeneous system research. BYOC is an open-source hardware framework that provides a scalable cache coherence system, that includes out-of-the-box support for four different ISAs (RISC-V 32-bit, RISC-V 64-bit, x86, and SPARCv9) and has been connected to ten different cores. The framework also supports multiple loosely coupled accelerators and is a fully working system supporting SMP Linux. The Transaction-Response Interface (TRI) introduced with BYOC has been specifically designed to make it easy to add in new cores

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Section: Resultssupporting

confidence: 78%

Byoc

Balkind

Lim

Schaffner

et al. 2020

Proceedings of the Twenty-Fifth International Conference on Architectural Support for Programming Languages and Operating Syste

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“…The Piton processor prototype 12,13 was manufactured in March 2015 on IBM's 32 nm SOI process with a target clock frequency of 1GHz. It features 25 tiles in a 5 × 5 mesh on a 6mm × 6mm (36 mm 2 ) die.…”

Section: The Princeton Piton Processormentioning

confidence: 99%

“…With Piton, we also produced the first detailed power and energy characterization of an open source manycore design implemented in silicon. 13 This included characterizing energy per instruction, NoC energy, voltage versus frequency scaling, thermal characterization, and memory system energy, among other properties. All of this was done in our lab, running on the Piton processor with the OpenPiton chipset implemented on FPGA.…”

Section: The Princeton Piton Processormentioning

confidence: 99%

“…OpenPiton enables research from the small to the large with demonstrated implementations from the slimmed-down, single-core PicoPiton, which is emulated on a $160 Xilinx Artix 7 at 29.5MHz, up to the 25-core Piton processor which targeted a 1GHz operating point and was recently validated and thoroughly characterized. 12,13 The OpenPiton platform shown in Figure 1 is a modern, tiled, manycore design consisting of a 64-bit architecture using the mature SPARC v9 ISA with P-Mesh: our scalable cache coherence protocol and network on chip (NoC). OpenPiton builds upon the industry-hardened, open-source OpenSPARC T1 15,1,18 core, but sports a completely scratchbuilt uncore (caches, cache-coherence protocol, NoCs, NoC-based I/O bridges, etc), a new and modern simulation framework, configurable and portable FPGA scripts, a complete set of scripts enabling synthesis and implementation of ready-to-manufacture chips, and full-stack multiuser Debian Linux support.…”

Section: Introductionmentioning

confidence: 99%

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OpenPiton

Balkind

McKeown

et al. 2019

Commun. ACM

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Industry is building larger, more complex, manycore processors on the back of strong institutional knowledge, but academic projects face difficulties in replicating that scale. To alleviate these difficulties and to develop and share knowledge, the community needs open architecture frameworks for simulation, chip design, and software exploration that support extensibility, scalability, and configurability, alongside an established base of verification tools and supported software. In this article, we present OpenPiton, an open source framework for building scalable architecture research prototypes from one core to 500 million cores. OpenPiton is the world's first open source, general-purpose, multithreaded manycore processor, and framework. OpenPiton is highly configurable, providing a rich design space spanning a variety of hardware parameters that researchers can change. OpenPiton designs can be emulated on FPGAs, where they can run full-stack multiuser Debian Linux. OpenPiton is designed to scale to very large core fabrics, enabling researchers to measure operating system, compiler, and software scalability. The mature codebase reflects the complexity of an industrial-grade design and provides the necessary scripts to build new chips, making OpenPiton a natural choice for computer-aided design (CAD) research. OpenPiton has been validated with a 25-core chip prototype, named Piton, and is bolstered by a validation suite that has thousands of tests, providing an environment to test new hardware designs while verifying the correctness of the whole system. OpenPiton is being actively used in research both internally to Princeton and in the wider community, as well as being adopted in education, industry, and government settings.

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“…However, these methods require extra ports in routers and additional wire resources between nodes, that are unfriendly to physical design. Owing to the routing complexity of high-radix networks, most system designers have opted for simpler topologies (such as ring or mesh) instead [11][12][13]. For these low-radix networks, reducing the latency of each router is an alternative approach.…”

Section: Introductionmentioning

confidence: 99%

A Latency-Optimized Network-on-Chip with Rapid Bypass Channels

Ma¹,

Gao²,

Gao³

et al. 2021

Micromachines

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Network-on-Chips with simple topologies are widely used due to their scalability and high bandwidth. The transmission latency increases greatly with the number of on-chip nodes. A NoC, called single-cycle multi-hop asynchronous repeated traversal (SMART), is proposed to solve the problem by bypassing intermediate routers. However, the bypass setup request of SMART requires additional pipeline stages and wires. In this paper, we present a NoC with rapid bypass channels that integrates the bypass information into each flit. In the proposed NoC, all the bypass requests are delivered along with flits at the same time reducing the transmission latency. Besides, the bypass request is unicasted in our design instead of broadcasting in SMART leading to a great reduction in wire overhead. We evaluate the NoC in four synthetic traffic patterns. The result shows that the latency of our proposed NoC is 63.54% less than the 1-cycle NoC. Compared to SMART, more than 80% wire overhead and 27% latency are reduced.

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Power and Energy Characterization of an Open Source 25-Core Manycore Processor

Cited by 27 publications

References 55 publications

Byoc

Byoc

OpenPiton

A Latency-Optimized Network-on-Chip with Rapid Bypass Channels

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