Power and performance simulator: ESP and its application for 100 MIPS/W class RISC design

Sato, Taichiro; Nagamatsu, M.; Tago, H.

doi:10.1109/lpe.1994.573197

Cited by 36 publications

(18 citation statements)

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“…Ong and Ynn [4] showed that the energy dissipation may drastically vary depending on the algorithms running on a dedicated hardware. A power and performance simulation tool for a RISC design has been developed by Sato et al [5]. Their tool can be used to conduct architecture-level optimizations.…”

Section: Related Researchmentioning

confidence: 99%

A Framework for Estimating and Minimizing Energy Dissipation of Embedded HW/SW Systems Permission to make digital/hard copy of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commerdal advantage, the copyright notice, the title of the publication and its date appear, and notice is given that copying is by permission of ACM, Inc. To copy otherwise, to republish, to post on servers or to redistribute to lists, requi

Li¹,

Henkel²

2002

Readings in Hardware/Software Co-Design

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Embedded system design is one of the most challenging tasks in VLSI CAD because of the vast amount of system parameters to fix and the great variety of constraints to meet. In this paper we focus on the constraint of low energy dissipation, an indispensable peculiarity of embedded mobile computing systems. We present the first comprehensive framework that simultaneously evaluates the tradeoffs of energy dissipations of software and hardware such as caches and main memory. Unlike previous work in low power research which focused only on software or hardware, our framework optimizes system parameters to minimize energy dissipation of the overall system. The trade-off between system performance and energy dissipation is also explored. Experimental results show that our Avalanche framework can drastically reduce system energy dissipation. IntroductionThe design of embedded systems is a challenging task for today's VLSI CAD environments. As opposed to a general purpose computing system, an embedded system performs just one particular application that is known a priori. Therefore, the system can be designed with respect to the particular application to have lower cost, higher performance, or be more energy-efficient. Energy efficiency is a hot topic in embedded system design. As mobile computing systems (e.g. cellular phones, laptop computers, video cams, etc.) become more popular, how to length the battery life of these systems becomes a critical issue.From the design process point of view, many of the embedded systems can be integrated on just one chip (systems on a chip) using core based design techniques. Previous work in core-based system design has mainly focused on performance and cost constraints. Some recent work has been presented in co-synthesis for low power [1,2]. However, the trade-off in energy dissipation among software 1 , memory and hardware has not yet been explored. This is a challenging and indispensable task for the design of low power embedded systems. Consider for example, that the use of a bigger cache can reduce the number of cache misses and speed up the software execution, which may cause less energy dissipation on the processor. On the other hand, a larger cache size also causes bigger switching capacitance for cache accesses and therefore increases the cache energy dissipation per access.In this paper we present our framework Avalanche, the first framework that explores the design space of hardware/software systems in terms of overall system energy dissipation. Since embedded system design usually has multiple constraints such as performance and power, our framework 1 We use the term software energy dissipation for the energy that is dissipated within a processor core. Permission to make digital/hard copy of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage, the copyright notice, the title of the publication and its date appear, and notice is given that copying is by pe...

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Section: Related Researchmentioning

confidence: 99%

A Framework for Estimating and Minimizing Energy Dissipation of Embedded HW/SW Systems Permission to make digital/hard copy of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commerdal advantage, the copyright notice, the title of the publication and its date appear, and notice is given that copying is by permission of ACM, Inc. To copy otherwise, to republish, to post on servers or to redistribute to lists, requi

Li¹,

Henkel²

2002

Readings in Hardware/Software Co-Design

View full text Add to dashboard Cite

show abstract

“…Ong and Ynn [3] have shown that the energy dissipation may drastically vary depending on the algorithms running on a processor. A power and performance simulation tool for a RISC design has been developed by Sato et al [4]. Their tool has been used by designers to conduct architectural-level optimizations.…”

Section: Related Researchmentioning

confidence: 99%

“…T 100% hit is the execution time of the program with an assumption of a 100% cache hit rate. 4 In the current state this model is implemented for a 33MHz SPARCLite processor. The total program execution time is modeled by:…”

Section: Software Energymentioning

confidence: 99%

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Energy-conscious HW/SW-partitioning of embedded systems: a case study on an MPEG-2 encoder

Henkel¹,

Li²

Proceedings of the Sixth International Workshop on Hardware/Software Codesign. (CODES/CASHE'98)

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Energy dissipation is a hot topic in the design of -especially mobile -embedded systems. This is because applications like digital video cameras, cellular phones etc. draw their current from batteries that spend a limited amount of energy only. In this paper we show that energy-conscious HW/SWpartitioning can lead to drastic reductions of energy dissipation of a whole embedded system. Subject of investigation is an MPEG-2 encoder. Therefore, we introduce our framework for estimating and optimizing system energy as well as all conducted design steps. The obtained results show energy savings up 59% while the performance remains approximately the same or becomes even slightly higher. As a main result, energy-conscious HW/SW-partitioning is a promising method to be deployed in addition to classical energy and/or power reduction methods.

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“…Some attempts have been made towards architectural level analysis of processors, where power cost of architectural modules, e.g. datapath execution units, control units, and memory elements, are assumed to be estimated average capacitance that will switch when the given module is activated [83,841. Statistical power models have been used in [14, 851 for functional modules, the activity of which are obtained through functional simulation.…”

Section: Precomputation-based Optimization For Low-powermentioning

confidence: 99%

Design of low power digital systems

Roy¹,

Roy²,

Chou³

Emerging Technologies: Designing Low Power Digital Systems

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With the increasing use of portable computing arid wireless communication systems, the power dissipation of digital and analog systems are of increasing concern. However, the design objectives to achieve a certain performance with ultralow power dissipation sometimes have conflicting requirements. In this chapter we will first consider in detail how power is dissipated in CMOS digital circuits, derive power estimation techniques for CMOS digital circuits, and will present both hardware and software design considerations for ultra low power dissipation. 2.

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Power and performance simulator: ESP and its application for 100 MIPS/W class RISC design

Cited by 36 publications

References 1 publication

Energy-conscious HW/SW-partitioning of embedded systems: a case study on an MPEG-2 encoder

Design of low power digital systems

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