Power aware VLSI routing using particle swarm optimization for green electronics

Abstract

Energy power dissipation is one of the most critical aspects of todays information society. The most obvious benefits of being Green are reduced environmental impact and cost savings. Reducing energy consumption of electronic devices and circuits .This paper deals with the particle swarm optimization approach for optimal power dissipation in VLSI interconnect driven routing technique. Interconnect power dissipation is a major challenging research problem in deep submicron (DSM) regime that affects the overall circuit performance. The Buffer Insertion, (Buffer) Sizing and Wire Sizing (BISWS) are considered for minimizing the power dissipation using interconnect wires. The shortest path constraints, buffer insert constraints and wire size constraints are considered for analysis the optimal power allocation is derived. The Particle swarm optimization algaritham can be used to efficiently estimate the power dissipation in the stages of the VLSI designs. It is observed that the power dissipation is optimal using the shortest path between source to sink.

A Survey on Steiner Tree Construction and Global Routing for VLSI Design

“…This wire size is inversely proportional to the power dissipation and buffer insertion is directly proportional to the power dissipation. Nallathambi and Rajaram [145] used PSO to consider buffer insertion, buffer size adjustment, and wire sizing to minimize interconnect power consumption. The shortest path constraints, buffer insertion constraints, and wire size constraints are considered for analysis and optimal power distribution.…”