2010 IEEE Energy Conversion Congress and Exposition 2010
DOI: 10.1109/ecce.2010.5618043
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Power-CAD: A novel methodology for design, analysis and optimization of Power Electronic Module layouts

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Cited by 35 publications
(17 citation statements)
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“…The performance of the optimized layout was assured better than the initial designs. With the presented design procedure, it is 9 times faster than the method in [6]. As shown in Fig.…”
Section: Examples Of Automatic Layout Designmentioning
confidence: 97%
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“…The performance of the optimized layout was assured better than the initial designs. With the presented design procedure, it is 9 times faster than the method in [6]. As shown in Fig.…”
Section: Examples Of Automatic Layout Designmentioning
confidence: 97%
“…12). Boundary element method based parasitic parameter calculation is utilized for fitness evaluation in [6] and it is the main cause for low speed with a large die number. To increase the optimization speed, the current conducting length is used to represent parasitic resistance and the surrounded area is used to represent the parasitic inductance [5].…”
Section: Layout Design Proceduresmentioning
confidence: 99%
See 1 more Smart Citation
“…However, the model is complex and difficult to run for a long time. In addition, some researchers attempted to extend widely used electrical simulators (e.g., Spice, Saber) to power semiconductors for electrothermal simulations by introducing lumped thermal impedance [15,16]. However, the precision of this method depends on the accuracy of both the circuit model itself For the application under transient overload extreme conditions, this article proposed a novel method of electrothermal cosimulation for high-power IGBT.…”
Section: Introductionmentioning
confidence: 99%
“…These models are simple, time efficient, and can be easily integrated in various circuit simulators (e.g. PLECS, Spice, Saber) [6]- [8]. However, there is still a deficiency for current Cauer and Foster models.…”
Section: Introductionmentioning
confidence: 99%