Power Consumption Analysis of BCD Adder using XPower Analyzer on VIRTEX FPGA

Verma, Gaurav; Mishra, Sumita; Singh, Surabhi; Shekhar, Sushant; Virdi, Sukhbani Kaur

doi:10.17485/ijst/2015/v8i18/77053

Cited by 6 publications

(3 citation statements)

References 9 publications

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“…In [4] authors have tried to scaled the capacitance value for energy efficient tera hertz and designed a Malayalam Unicode Reader on Virtex-6 FPGA. In [5] analysis of power consumption of BCD Adder is tested by the authors using FPGA on Xilinx ISE Design software. In [6] authors have designed a routing switch which uses low power on FPGA.…”

Section: Related Workmentioning

confidence: 99%

Power Efficient UART Desing Using Capactive Load on Different Nanometer Technology FPGA

Kumar

Hussain²,

Pandey³

2019

GJET

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In this paper, we are changing the capacitance of the UART and observing the power at different value of capacitance. As we are changing the capacitance of UART not only power but the maximum temperature and junction temperature also get affected. As the value of capacitance increases and reaches 50000 pf or above in Virtex-4, Virtex-5, Virtex-6 the capacitor of the UART burns out and for Spartan-3 and Spartan-6 when capacitance value goes to 5000 pf or above the capacitor of the UART burns out. Burning of capacitor disturbs the communication of UART over longer distance. In this paper power analysis is done on Xilinx ISE Design 14.1 and the UART code is written in Verilog Hardware Description Language. Power analysis is done by changing the capacitance of the capacitor from 5 pf to 50,000 pf at different nanometer technology based FPGA that are Virtex-4, Virtex-5, Virtex-6, Spartan-3 and Spartan-6 respectively.

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Section: Related Workmentioning

confidence: 99%

Power Efficient UART Desing Using Capactive Load on Different Nanometer Technology FPGA

Kumar

Hussain²,

Pandey³

2019

GJET

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“…The evolution of the MOCLA adder has been compared with conventional CLA adders [5] , [6] . The detailed comparison results of CLA adders are shown in Table 1 .The binary coded decimal adders are designed with the help of carry skip adder for improving speed in decimal arithmetic logic unit [1] , [2] , [3] , [4] , [5] , [6] . The two input multiplexers used in this adder were realized using only two transistors for area reduction [7] .…”

Section: Datamentioning

confidence: 99%

Power analysis data set for 4-Bit MOCLA adder

Kandasamy

2018

Data in Brief

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In order to reduce the silicon area of the chip and optimize the power of arithmetic circuits, this paper proposes a low power carry look-ahead BCD (Binary Coded Decimal) adder which uses a four bit MOCLA (Multiplexer and Or gate based Carry Look Ahead Adder) that forms the basic building block. This proposed MOCLA style uses a 2 input MUX, OR gate and GDI (Gate Diffusion Input) based full adder and PG units and it is used for achieving low power in BCD adder circuits.

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“…Verma et al [17] presented low power techniques which can be applied for different target platforms at different levels of design hierarchy. Verma et al [18] performed power analysis by performing scaling of parameters like voltage, frequency and load capacitance and airflow for power optimization.…”

Section: Literature Surveymentioning

confidence: 99%

Matlab Interface For Power And Timing Analysis Of Digital Circuits

Verma¹,

Abhishek²,

Chauhan³

et al. 2017

GJET

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Due to advent in CMOS technology, it has become possible now to put millions of transistors on a single chip of silicon. This has drastically increased the performance of the device and it can do much faster operations. But on the other side, putting more transistors on a silicon chip triggering the problem of increased power consumption. So, it becomes a bottleneck for the designer to choose in between performance and power consumption. Particularly, for reconfigurable hardware like FPGAs the situation is worst and demands concern. So, this paper presents some optimization techniques that are applied on FPGAs at different levels of abstraction. Some benchmark circuits like ALU, Register, Counter and RAM are used for experimental measurements to validate the results. After simulation and power analysis of benchmark circuits at different frequencies, a power aware utility software is developed that performs optimization of power keeping performance in consideration at a given frequency for the selected FPGA. The circuits have been implemented using VHDL as the hardware description language and simulation is carried out using Xilinx ISE 14.1 by targeting Virtex-4, 5 and Artix-7 FPGA.

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Power Consumption Analysis of BCD Adder using XPower Analyzer on VIRTEX FPGA

Cited by 6 publications

References 9 publications

Power Efficient UART Desing Using Capactive Load on Different Nanometer Technology FPGA

Power Efficient UART Desing Using Capactive Load on Different Nanometer Technology FPGA

Power analysis data set for 4-Bit MOCLA adder

Matlab Interface For Power And Timing Analysis Of Digital Circuits

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