Power consumption of sequential CMOS circuits using Logic Pictures

Fouda, Moatasem; Abdelhalim, M. B.; Amer, Hassanein H.

doi:10.1109/bec.2010.5631515

Cited by 3 publications

(3 citation statements)

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“…Clearly, designing more and more sophisticated systems and wireless devices requires constant development and compiling new methods used for designing digital systems able to save energy. Nowadays, the greatest importance is put on CMOS technology, in which optimization at the level of gates is not sufficient [1] - [4], but is required at each phase of the project including software development [5] - [9].…”

Section: Introductionmentioning

confidence: 99%

Power Consumption Analysis of Microprocessor Unit Based on Software Realization

Maćkowski

Niezabitowski

2015

2015 20th International Conference on Control Systems and Computer Science

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With the advent of portable and high density microelectronic devices, the minimization of power consumption in CMOS VLSI circuits is becoming a critical concern. An embedded system is a combination of electronic hardware and software and sometimes additional parts designed to perform a dedicated function. In many cases system (microprocessor) must monitor the amount of power it uses and take appropriate steps to save the battery life. There are several methods to save power consumption of microprocessor unit including: clock control, power-sensitive processors, low-voltage and circuit shutdown. The effect of reducing power consumption can be achieved either by hardware or software optimization. This paper presents the software level power consumption analysis of MCU, focusing mainly on instruction and data realization.

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Section: Introductionmentioning

confidence: 99%

Power Consumption Analysis of Microprocessor Unit Based on Software Realization

Maćkowski

Niezabitowski

2015

2015 20th International Conference on Control Systems and Computer Science

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“…The main advantage of this method is that it is deterministic and the simulations required are much less time-consuming than exhaustive simulations. The logic picture concept was modified in [11] to calculate the average power consumption for sequential circuits. In [12], the method was generalized and extended to calculate the maximum power consumption for sequential circuits including all types of Flip-Flops and their internal nodes power consumption; it was also shown how the tool could be used for design space exploration to select the appropriate Flip-Flop that consumed less power.…”

Section: Introductionmentioning

confidence: 99%

“…In [12], the method was generalized and extended to calculate the maximum power consumption for sequential circuits including all types of Flip-Flops and their internal nodes power consumption; it was also shown how the tool could be used for design space exploration to select the appropriate Flip-Flop that consumed less power. While the method in [10][11][12] is accurate, it assumed that no propagation delay was associated with logic gates, i.e., zero-delay model.…”

Section: Introductionmentioning

confidence: 99%

Logic Picture-Based Dynamic Power Estimation for Unit Gate-Delay Model CMOS Circuits

Ahmed¹,

Abu-Elyazeed²,

Abdelhalim³

et al. 2013

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In this research, a fast methodology to calculate the exact value of the average dynamic power consumption for CMOS combinational logic circuits is developed. The delay model used is the unit-delay model where all gates have the same propagation delay. The main advantages of this method over other techniques are its accuracy, as it is deterministic and it requires less computational effort compared to exhaustive simulation approaches. The methodology uses the Logic Pictures concept for obtaining the nodes’ toggle rates. The proposed method is applied to well-known circuits and the results are compared to exhaustive simulation and Monte Carlosimulation methods

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