Power-Driven Routing-Constrained Scan Chain Design

Abstract

Scan-based architectures, though widely used in modern designs, are expensive in power consumption. In this paper, we present a new technique that allows to design power-optimized scan chains under a given routing constraint. The proposed technique is a three-phase process based on clustering and reordering of scan cells in the design. It allows to reduce average power consumption during scan testing. Owing to this technique, short scan connections in scan chains are guaranteed and congestion problems in the design are avoided.

Pattern-directed circuit virtual partitioning for test power reduction

“…For IS-CAS'89 circuits, the fully-specified test patterns used in our experiments are the low-capture-power patterns in [24] (for stuck-at tests) and [25] (for broad-side delay tests); while for ITC'99 circuits, they are generated with a commercial ATPG tool. In addition, we generate the scan cell placement Paper 25.2 INTERNATIONAL TEST CONFERENCE with a commercial physical design tool and make use of the algorithms in [2] to route our scan chains for scan chain routing cost comparison. Finally, the size difference constraint d size for the partitioned subcircuits is set to be 15% in our experiments; while the weighting factor w in Eq.…”

“…Although the proposed pattern-directed circuit virtual partitioning technique does not require to rerun ATPG and add test wrappers to ensure no fault coverage loss, it is not entirely cost-free, especially from the scan routing cost point of view. To compare the scan chain length before and after partitioning, we use the routing-constrained scan chain design algorithm in [2], which first divides the circuit into several sub-regions and routes them separately and then connect them in a "snake-like" way. We assume there exist two scan chains for the original circuit and each partitioned subcircuit contains a single scan chain.…”

“…In order to effectively apply more high-power patterns within a single partition, we would like to let the high-power patterns to have as few care-bits as possible. Therefore, if a fault is detected by multiple test patterns, we will let the test pattern with the lowest scan capture power to cover it 2 The scan capture transition count of a test pattern is defined as the total number of transitions of all circuit nodes in scan capture mode, including both FFs and combinational gates. (we do not consider N-detect here for the sake of simplicity in discussion).…”

“…It is possible that the test power consumption exceeds the circuit's power rating in both shift mode and capture mode. Techniques based on scan chain manipulation (e.g, [1,2,16,26]) are very effective in reducing scan shift power, but does not help in reducing scan capture power. There are also some other approaches that reduce the switching activities of the CUT by taking advantage of the 'don't-care' bits in test cubes, e.g., the low-power automatic test pattern generation (ATPG) techniques in [6,22] and the test vector manipulation methodologies in [7,15,17,25].…”