Power-Efficient Accelerator Design for Neural Networks Using Computation Reuse

Yasoubi, Ali; Hojabr, Reza; Modarressi, Mehdi

doi:10.1109/lca.2016.2521654

Cited by 28 publications

(15 citation statements)

References 12 publications

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“…PACMAN uses a simulated annealing algorithm to search for the best partitioning plan. A variety of previous studies have examined neural network accelerators in which parameters such as reduced power consumption [23,24], increased throughput [25,26], and the use of memory bandwidth for information processing are evaluated. A variety of previous studies have examined neural network accelerators in which parameters such as reduced power consumption [23,24], increased throughput [25,26], and the use of memory bandwidth for information processing are evaluated [27].…”

Section: Related Workmentioning

confidence: 99%

Providing an Adaptive Routing along with a Hybrid Selection Strategy to Increase Efficiency in NoC‐Based Neuromorphic Systems

Trik

Mozaffari

Bidgoli

2021

Computational Intelligence and Neuroscience

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Effective and efficient routing is one of the most important parts of routing in NoC-based neuromorphic systems. In fact, this communication structure connects different units through the packets routed by routers and switches embedded in the network on a chip. With the help of this capability, not only high scalability and high development can be created, but by decreasing the global wiring to the chip level, power consumption can be reduced. In this paper, an adaptive routing algorithm for NoC-based neuromorphic systems is proposed along with a hybrid selection strategy. Accordingly, a traffic analyzer is first used to determine the type of local or nonlocal traffic depending on the number of hops. Then, considering the type of traffic, the RCA and NoP selection strategies are used for the nonlocal and local strategies, respectively. Finally, using the experiments that performed in the simulator environment, it has been shown that this solution can well reduce the average delay time and power consumption.

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Section: Related Workmentioning

confidence: 99%

Providing an Adaptive Routing along with a Hybrid Selection Strategy to Increase Efficiency in NoC‐Based Neuromorphic Systems

Trik

Mozaffari

Bidgoli

2021

Computational Intelligence and Neuroscience

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“…For permanent fault, [3] proposes a fault-aware mapping technique to minus the permanent fault in MAC units. For power-efficient technology, [4] proposes a computation re-use-aware neural network technique to reuse the weight by constructing a computational reuse table. [5] uses approximate a computing technique to retrain the network for getting the resilient neurons.…”

Section: Introductionmentioning

confidence: 99%

“…These articles focus on fault tolerance technology specifically. Some of them such as [4,5] address the relationship between accuracy and power-efficient together but lack computation ability information. Besides these listed articles, there are still many published works targeting fault tolerance in recent years.…”

Section: Introductionmentioning

confidence: 99%

Low-power ultra-small Edge AI Accelerators for Image Recognition with Convolution Neural Networks: Analysis and Future Directions

Lin¹,

Adetomi²,

Arslan³

2021

Preprint

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Edge AI accelerators have been emerging as a solution for near customers’ applications in areas such as unmanned aerial vehicles (UAVs), image recognition sensors, wearable devices, robotics, and remote sensing satellites. These applications not only require meeting performance targets but also meeting strict reliability and resilience constraints due to operations in harsh and hostile environments. Numerous research articles have been proposed, but not all of these include full specifications. Most of these tend to compare their architecture with other existing CPUs, GPUs, or other reference research. This implies that the performance results of the articles are not comprehensive. Thus, this work lists the three key features in the specifications such as computation ability, power consumption, and the area size of prior art edge AI accelerators and the CGRA accelerators during the past few years to define and evaluate the low power ultra-small edge AI accelerators. We introduce the actual evaluation results showing the trend in edge AI accelerator design about key performance metrics to guide designers on the actual performance of existing edge AI accelerators’ capability and provide future design directions and trends for other applications with challenging constraints.

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“…For permanent faults, Reference [3] proposes a fault-aware mapping technique to minus the permanent fault in MAC units. For powerefficient technology, Reference [4] proposes a computation re-use-aware neural network technique to reuse the weight by constructing a computational reuse table. Reference [5] uses an approximate computing technique to retrain the network for getting the resilient neurons.…”

mentioning

confidence: 99%

“…These articles focus on fault tolerance technology specifically. Some of them address the relationship between accuracy and power-efficient together but lack computation ability information [4,5]. Besides these listed articles, there are still many published works targeting fault tolerance in recent years, which indicates that the edge AI with fault tolerance is the trend.…”

mentioning

confidence: 99%

Low-Power Ultra-Small Edge AI Accelerators for Image Recognition with Convolution Neural Networks: Analysis and Future Directions

2021

View full text Add to dashboard Cite

Edge AI accelerators have been emerging as a solution for near customers’ applications in areas such as unmanned aerial vehicles (UAVs), image recognition sensors, wearable devices, robotics, and remote sensing satellites. These applications require meeting performance targets and resilience constraints due to the limited device area and hostile environments for operation. Numerous research articles have proposed the edge AI accelerator for satisfying the applications, but not all include full specifications. Most of them tend to compare the architecture with other existing CPUs, GPUs, or other reference research, which implies that the performance exposé of the articles are not comprehensive. Thus, this work lists the essential specifications of prior art edge AI accelerators and the CGRA accelerators during the past few years to define and evaluate the low power ultra-small edge AI accelerators. The actual performance, implementation, and productized examples of edge AI accelerators are released in this paper. We introduce the evaluation results showing the edge AI accelerator design trend about key performance metrics to guide designers. Last but not least, we give out the prospect of developing edge AI’s existing and future directions and trends, which will involve other technologies for future challenging constraints.

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Power-Efficient Accelerator Design for Neural Networks Using Computation Reuse

Cited by 28 publications

References 12 publications

Providing an Adaptive Routing along with a Hybrid Selection Strategy to Increase Efficiency in NoC‐Based Neuromorphic Systems

Providing an Adaptive Routing along with a Hybrid Selection Strategy to Increase Efficiency in NoC‐Based Neuromorphic Systems

Low-power ultra-small Edge AI Accelerators for Image Recognition with Convolution Neural Networks: Analysis and Future Directions

Low-Power Ultra-Small Edge AI Accelerators for Image Recognition with Convolution Neural Networks: Analysis and Future Directions

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