Power-efficient and slew-aware three dimensional gated clock tree synthesis

Lin, Minghao; Sun, Heming

doi:10.1109/vlsi-soc.2016.7753535

Cited by 5 publications

(2 citation statements)

References 15 publications

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“…The pre-route process is arbitrary logic placement before the real route process. After the placement process, the clock is physically connected, and clock skew occurs as logic is placed respectively [17]. This study assumes that it does not consider timing constraints or parasitic components like R, C, cell strength, etc.…”

Section: Pre-route Processmentioning

confidence: 99%

Shallow Clock Tree Pre-Estimation for Designing Clock Tree Synthesizable Verilog RTLs

Kwon,

Park

2023

Electronics

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Clock tree synthesis (CTS) is an important process in determining overall chip timing and power consumption. The CTS is also a time-consuming process for checking the clock tree. If the chip design and specification do not match, the CTS result will be wrong. Many users use licensed electronic design automation (EDA) tools like Synopsys, and Cadence to carry out accurate chip verification. However, when using a licensed EDA tool, it is difficult to change the function and confirm the overall process in detail. If the design is wrong, the expected cost is doubled, as it will be necessary to modify the design and check all processes for verification. Currently, it cannot check the synthesizability of the clock tree on the placement and route process using only RTL. The main purpose of this study is to predict the CTS result of pre-estimation roughly using an RTL source placing temporary logics using random buffer insertion before the route process: then the incorrectly designed part can be freely modified because the CTS result can be known in advance. Experimental results showed that this research achieves an increase in inserted buffer area by about 10%, the standard deviation of clock skew achieves zero clock skew after shallow CTS, and clock frequency increases by about 10%. This paper contributes to optimizing clock tree implementation by conducting the pre-route process before using the CTS tool. Also, our approach not only minimizes resource usage but also optimizes CTS for the RTL structure. It holds considerable value in enhancing the efficiency and performance of integrated circuits.

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Section: Pre-route Processmentioning

confidence: 99%

Shallow Clock Tree Pre-Estimation for Designing Clock Tree Synthesizable Verilog RTLs

Kwon,

Park

2023

Electronics

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“…have developed and patented the method for identifying clock entry points for each partition to perform clock tree synthesis at top level and then created virtual leaf points for grids to determine the clock skew and latency Lai et al (2007). suggested and patented the method for obtaining synthesis of the low power clock tree by using buffer insertion, resizing and removal technique for the VLSI circuits Lin et al (2016). have proposed 3D gated CTS for achieving slew rate, minimization of skew and…”

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confidence: 99%

Improved result of TSV and Slew aware 3D Gated Clock Tree Synthesis using charge recycling configuration

Rajalakshmi¹,

Ramesh²,

Sivakumar³

2021

3C Tecnología

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In physical design of Integrated Circuits (ICs) especially after placement, Clock Tree Synthesis (CTS) plays a major part in the general chip efficiency. Three Dimensional Integrated Circuits (3D ICs) based on Through Silicon Via (TSV) present a major challenge for IC developers. 3D gated CTS on the TSV-TSV coupling model is an effective approach to reduce power, delay and clock skew. This paper proposes a slew aware TSV arrangement with clock gating logic in 3D CTS. It consists of the following 3 phases, viz., TSV clock tree synthesis, gated logic insertion in 3D CTS and charge recycling configuration for power gating structures. Unlike the previous methods available in literature, the proposed TSV aware 3D clock tree synthesis performs with TSV model in the beginning followed by the gated logic. Multiple experiments were conducted on the bench mark circuits and it can be inferred that, compared with the existing 3D CTS method on TSV-TSV coupling model, the proposed 3D gated CTS method on TSV model is simple and efficient for practical applications achieving average reduction in the clock skew and power.

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A low power high efficient radio frequency clock generator for bio-implants

Katikala

Nelakuditi

2017

2017 2nd International Conference on Communication and Electronics Systems (ICCES)

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Power-efficient and slew-aware three dimensional gated clock tree synthesis

Cited by 5 publications

References 15 publications

Shallow Clock Tree Pre-Estimation for Designing Clock Tree Synthesizable Verilog RTLs

Shallow Clock Tree Pre-Estimation for Designing Clock Tree Synthesizable Verilog RTLs

Improved result of TSV and Slew aware 3D Gated Clock Tree Synthesis using charge recycling configuration

A low power high efficient radio frequency clock generator for bio-implants

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